Patrick Schmidt, M.Sc
- Group: Prof. Becker
- Room: 217
CS 30.10 - Phone: +49 721 608-41315
- patrick schmidt2 ∂does-not-exist.kit edu
- Engesserstraße 5
76131 Karlsruhe
High-Level Synthesis for AI Accelerators
In order to reduce the design time of AI accelerators, the field of High-Level Synthesis has gained traction. It moves the design from traditional HDL languages to a more abstract level, such as SystemC or C++, and enable the designer to rapidly evaluate different architectures. Since AI accelerators are very data path heavy, they are a good fit for this way of modelling them, as they can easily be described algorithmically. Through these methods, designers can focus on the architecture while low-level modelling, such as pipelining and interfaces, can be handled by the tools.
Compiling Neural Networks
Recent years have shown a large amount of novel hardware designs to effectively accelerate different kinds of neural networks. However, the tooling to deploy these networks on the hardware has been lacking behind. To address this, dedicated compilers for neural networks are necessary. Specifically, MLIR is a promising tool to enable the rapid development of optimizing compiler stacks for a wide range of hardware designs. It provides a large amount of necessary infrastructure and enables the modelling of custom hardware operations.
System-Level Design Evaluation
The most critical aspect of AI accelerators is not the available compute power, but the bandwidth needed to feed the compute engines with sufficient data. Enabling a full-stack evaluation of compute platform is therefore a crucial task. To support this, Architecture Design Languages can be used to provide an abstract model of the system and to generate a simulation platform. Coupled with a compiler, this provides a powerful tool for system analysis and evaluation.
| Title | Type |
|---|---|
| Machine learning compiler for embedded systems | Masterarbeit |
| Compiler-Based Integration of Neural Network Accelerators | Masterarbeit |
| Concept and development of high-performance hardware accelerators for neural networks | Bachelor/Master thesis |
| Parallel result validation of AI accelerators using most neuron activation monitor | Masterarbeit |
Publications
Kreß, F.; Hoefer, J.; Lin, Q.; Schmidt, P.; Zhu, Z.; Zhu, Y.; Harbaum, T.; Wang, Y.; Becker, J.
2025. 2025 26th International Symposium on Quality Electronic Design (ISQED), 23rd-24th April 2025, San Francisco, 1–8, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISQED65160.2025.11014471
Mojumder, S.; Friedrich, S.; Matúš, E.; Fettweis, G.; Lueders, M.; Friedrich, M.; Renke, O.; Blume, H.; Hoefer, J.; Schmidt, P.; Becker, J.; Grantz, D.; Kock, M.; Benndorf, J.; Fasfous, N.; Mori, P.; Voegel, H.-J.; Ahmadifarsani, S.; Kontopoulos, L.; Schlichtmann, U.; Bierzynski, K.
2024. 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), Lund, Sweden, 29-30 October 2024, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/NorCAS64408.2024.10752454
Schmidt, P.; Topko, I.; Stammler, M.; Harbaum, T.; Becker, J.; Berner, R.; Ahmed, O.; Jagielski, J.; Seidler, T.; Abel, M.; Kreutzer, M.; Kirschner, M.; Betancourt, V. P.; Sehm, R.; Groth, L.; Neskovic, A.; Meyer, R.; Mulhem, S.; Berekovic, M.; Probst, M.; Brosch, M.; Sigl, G.; Wild, T.; Ernst, M.; Herkersdorf, A.; Aigner, F.; Hommes, S.; Lauer, S.; Seidler, M.; Raste, T.; Bozic, G. S.; Ceberio, I. I.; Hassan, M.; Mayer, A.
2024. 27th Design, Automation and Test in Europe Conference and Exhibition (DATE 2024), 6 S., Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/DATE58400.2024.10546796
Schmidt, P.; Pfau, J.; Hotfilter, T.; Stammler, M.; Harbaum, T.; Becker, J.
2024. 2024 IEEE 37th International System-on-Chip Conference (SOCC), Dresden, 16th-19th September 2024, 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC62300.2024.10737723
Stammler, J. M.; Hoefer, J.; Schmidt, P.; Harbaum, T.; Becker, J.
2024. 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 656 – 660, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISVLSI61997.2024.00125
Neu, M.; Karle, C.; Schmidt, P.; Höfer, J.; Harbaum, T.; Becker, J.
2024. IEEE 37th International System-on-Chip Conference (SOCC 2024), 6 S., Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC62300.2024.10737798
Schmidt, P.; Becker, J.
2024. 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Orlando, 5th-8th May 2024, 241 – 242, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/FCCM60383.2024.00055
Stammler, M.; Sidorenko, V.; Kreß, F.; Schmidt, P.; Becker, J.
2024. 2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapur, 18th-21st December 2023, 97–104, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MCSoC60832.2023.00022
Stammler, M.; Höfer, J.; Kraus, D.; Schmidt, P.; Hotfilter, T.; Harbaum, T.; Becker, J.
2023. Procedia Computer Science, 222, 499 – 508. doi:10.1016/j.procs.2023.08.188
Kreß, F.; Sidorenko, V.; Schmidt, P.; Hoefer, J.; Hotfilter, T.; Walter, I.; Harbaum, T.; Becker, J.
2023. Computer Networks, 229, Article no: 109759. doi:10.1016/j.comnet.2023.109759
Kreß, F.; Pfau, J.; Kempf, F.; Schmidt, P.; He, Z.; Harbaum, T.; Becker, J.
2023. 2023 IEEE Nordic Circuits and Systems Conference (NorCAS), 31st October - 1st November 2023, Aalborg, Denmark, 1–7, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/NorCAS58970.2023.10305469
Chu, A.; Hermann, C. M.; Silz, J.; Pfau, J.; Barón, K. M.; Anantharajaiah, N.; Schmidt, P.; Hotfilter, T.; Xie, X.; Becker, J.; Kallfass, I.; Roth-Stielow, J.; Stork, W.
2023. IEEE EUROCON 2023 - 20th International Conference on Smart Technologies, 665–670, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/EUROCON56442.2023.10199076
Hotfilter, T.; Schmidt, P.; Höfer, J.; Kreß, F.; Harbaum, T.; Becker, J.
2023. DroneSE and RAPIDO: System Engineering for constrained embedded systems, 73–78, Association for Computing Machinery (ACM). doi:10.1145/3579170.3579258