Compiler-Based Integration of Neural Network Accelerators

Context 

In recent years, the demand for neural network implementations in embedded systems has risen sharply. Real-time neural networks are playing an increasingly important role in signal processing, particularly in the divisions of radar, experimental physics, and communications technology. At ITIV, we are therefore conducting research in several projects on the automated hardware implementation of various network architectures.

Tasks 

In recent years, frameworks for the automated implementation of neural networks on FPGAs have become established. However, toolchains such as hls4ml or FINN quickly reach their limits, especially when novel network architectures need to be investigated. The use of software compilers for hardware optimization promises new possibilities in the department of high-level synthesis. These enable optimizations of both the entire network architecture and the individual layers. The target of this thesis is the implementation of an application-specific network architecture using high-level synthesis for a freely chosen use case.

Requirements

• Experience with C/C++
• Basic experience with Verilog or high-level synthesis
• Interest in implementing neural networks in embedded systems