Johannes Pfau, M. Sc.

Johannes Pfau, M. Sc.

  • Engesserstraße 5
    76131 Karlsruhe

Research interests

FPGA Architecture and Toolchain Research

Novel semiconductor technologies and increasing demand for low power reconfigurable hardware demands changes in the system architecture of FPGA devices. Here, replacing commonly used lookup tables with in-memory-computing cells or universal logic modules requires changes in both architecture and toolchain, as synthesizing applications for such FPGAs calls for specialized algorithms. Similar challenges arise when dealing with localized power management in power regions: Synthesis tools need to specially handle these regions to enable power reduction benefits in user applications.

FPGA Beamforming Application Design

To broaden understanding of the environment in regards to the Bio-, Geo-, Cryo- and Hydrosphere, space agencies investigate novel space-borne monitoring solutions for dynamical processes on earth’s surface. The satellites employed have to reduce the massive amount of radar data received before transmitting it back to earth, a task well suited for FPGA data processing. Moving the previously analog beamforming completely into digital FPGA domain, we reduce system complexity and at the same time enable integration of further data compression algorithm in the system.


FPGA High-Throughput Data Acquisition

As part of initial development plans for 6G mobile communication, test fields will be set up with initial prototypes and demonstrator devices. Tests will generate massive amounts of data received by prototype antennas, which will need to be stored for further investigation. Analog/Digital conversion and further flexible processing is enabled by RFSoC systems, a combination of A/D converter, FPGA and CPU. To enable storage of the data, multiple 100 Gbit/s links from multiple RFSoC boards need to be synchronized, transferred to server farms and saved onto storage systems.


Supervised student works (selection)

  • BA: “Evaluation und Adaption von Open-Source FPGA-Architektur Frameworks“
  • SA: “Power Management Techniques in FPGA Architectures”
  • BA: “Design and Evaluation of Manual Placement Techniques for V-FPGA Tiles on FPGA”
  • BA: “Design and Evaluation of Hard-Logic Adder Extensions for Virtual FPGAs”
  • MA: “Designing a Framework to Evaluate the Performance of Region-based FPGA Power Management Using VPR”
  • MA: “Entwurf einer dynamisch aktualisierbaren Filterarchitektur für Digitales Beamforming mit hohem Datendurchsatz”
  • BA: “Implementation of a Data-Driven, Semi-Autonomous Control for the KIT Prosthetic Hand”


Journal Articles
Conference Papers
A hardware/software co-design approach to prototype 6G mobile applications inside the GNU Radio SDR Ecosystem using FPGA hardware accelerators
Karle, C. M.; Kreutzer, M.; Pfau, J.; Becker, J.
2022. HEART2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba Japan, June 9 - 10, 2022, 33–41, Association for Computing Machinery (ACM). doi:10.1145/3535044.3535049
Journal Articles
From MOSFETs to Ambipolar Transistors: Standard Cell Synthesis for the Planar RFET Technology
Reuter, M.; Pfau, J.; Krauss, T. A.; Becker, J.; Hofmann, K.
2021. IEEE transactions on circuits and systems / 1, 68 (1), 114–125. doi:10.1109/TCSI.2020.3035889
Conference Papers
Designing Universal Logic Module FPGA Architectures for Use With Ambipolar Transistor Technology
Pfau, J.; Reuter, M.; Hofmann, K.; Becker, J.
2021. 2020 International Conference on Field-Programmable Technology (ICFPT), Maui, HI, USA, 09-11 December 2020, 165–173, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ICFPT51103.2020.00031
Evaluation of Different Manual Placement Strategies to Ensure Uniformity of the V-FPGA
Pfau, J.; Zaki, P. W.; Becker, J.
2021. Applied Reconfigurable Computing. Architectures, Tools, and Applications: 17th International Symposium, ARC 2021, Virtual Event, June 29–30, 2021, Proceedings. Ed.: S. Derrien, 35–49, Springer Verlag. doi:10.1007/978-3-030-79025-7_3
Conference Papers
A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s
Pfau, J.; Reuter, M.; Harbaum, T.; Hofmann, K.; Becker, J.
2020. 2019 32nd IEEE International System-on-Chip Conference (SOCC), Singapore, 3-6 Sept. 2019, 294–299, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC46988.2019.1570548289
Towards Ambipolar Planar Devices: The DeFET Device in Area Constrained XOR Applications
Reuter, M.; Pfau, J.; Krauss, T. A.; Moradinasab, M.; Schwalke, U.; Becker, J.; Hofmann, K.
2020. Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems (LASCAS), San Jose, Costa Rica, February 15-28, 2020, Article No. 9069043, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/LASCAS45839.2020.9069043
Conference Papers
From MOSFETs to Ambipolar Transistors: A Static DeFET Inverter Cell for SOI
Reuter, M.; Krauss, T. A.; Moradinasab, M.; Pfau, J.; Schwalke, U.; Becker, J.; Hofmann, K.
2019. Proceedings. 2019 IEEE Asia Pacific Conference on Circuits and Systems : Royal Orchind Sheraton Hotel and Towers Bangkok, Thailand, November 11-14, 2019, 113–116, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/APCCAS47518.2019.8953083
Conference Papers
Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems
Pfau, J.; Figuli, S. P. D.; Bähr, S.; Becker, J.
2018. Applied Reconfigurable Computing - Architectures, Tools, and Applications, Proceedings of the 14th International Symposium, ARC 2018, Santorini, Greece, 2nd - 4th May 2018. Ed.: Nikolaos Voros, 615–626, Springer. doi:10.1007/978-3-319-78890-6_49
Journal Articles
Development of a Latency Optimized Communication Device for WAVE and SAE Based V2X-Applications
Pistorius, F.; Lauber, A.; Pfau, J.; Klimm, A.; Becker, J.
2016. SAE technical papers, 2016-April, 1–11. doi:10.4271/2016-01-0150