Hardware Modeling and Simulation
- Type: Vorlesung (V)
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Chair:
KIT-Fakultäten - KIT-Fakultät für Elektrotechnik und Informationstechnik - Institut für Technik der Informationsverarbeitung
KIT-Fakultäten - KIT-Fakultät für Elektrotechnik und Informationstechnik - Semester: WS 22/23
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Time:
ab 25.10.2023
Mittwochs 11:30 - 13:00, wöchentlich
30.10 Nachrichtentechnik-Hörsaal (NTI)
30.10 Nachrichtentechnik, Institutsgebäude (EG)
- Lecturer:
- SWS: 2
- Lv-no.: 2311608
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Information:
Presence
Presentation language | English |
Hardware Modeling and Simulation
Recommendations
Basic knowledge of digital technology is an advantage.
Objectives
Upon completion of the module, students will have basic knowledge of the design process of mechatronic systems using simulators, for both digital and analog circuit parts. Likewise, knowledge of cross-domain models in VHDL-AMS that include mixed digital, analog, and/or mechanical parts will be present. Students understand the fundamentals of fault simulations for verifiability of fabricated circuits and are able to derive test vectors. They will be able to derive OBDDs to verify the functional equivalence of two different models of digital circuits.
In addition, students have basic and detailed knowledge of the hardware description language VHDL. They are able to model circuit parts and consider the specifics of the timing behavior of modeled components. They are able to create testbenches for models to initiate functional and timing verification.
Contents
The support of electronic circuit design by CAE tools, which have spread rapidly in recent years, has resulted in a significant acceleration of the entire design process. In this lecture the basic design of electronic systems using CAE tools and the use of hardware description languages will be considered. The step-by-step approach through levels of abstraction will be taught. Proof methods for the correctness of designs will be discussed as well as the requirements for industrial design automation systems.