• Project group:

    Prof. Becker

  • Startdate:


  • Enddate:


PARFAIT: Power-aware AmbipolaR Fpga ArchITecture


From digital circuit prototyping to reconfigurable hardware accelerators, FPGAs can be used in a wide range of applications. However, their performance is limited significantly by chip heating resulting from their power consumption, and by high signal propagation delays in the interconnect network.

DeFET transistor technology is a promising means to face these problems. Using additional gates, it is possible to adjust transistor timing and power consumption and to switch between n- and p-channel characteristics (ambipolarity). This opens up new possibilities in FPGA architecture design, which are investigated in this project.

This project covers enhancing and analyzing DeFETs, determining new approaches in circuit design, and developing new FPGA architectures using DeFETs. ITIV focuses on improving interconnects and routing by bi-directional use of transmission lines. Additionally, the (dynamic) optimization of signal propagation delay and power dissipation by fine-grain adjustment of the threshold voltage is investigated, among others. This affects the overlying FPGA architecture, where new optimized approaches are considered in close cooperation with the project partners.