Hardware Synthesis and Optimization

  • Type: Lecture (V)
  • Chair: KIT Department of Electrical Engineering and Information Technology
  • Semester: SS 2026
  • Time:

    Every other Monday, 11:30 a.m. – 1:00 p.m.

    Starting April 20, 2026

    Through July 27, 2026

    In Room 20.40, Architecture Building, Lecture Hall 9

    20.40 Architecture Building (1st floor)

    Weekly on Wednesdays, 3:45–5:15 p.m.

    Starting April 22, 2026

    Through July 29, 2026

    In 20.40 Architecture Lecture Hall No. 9

    20.40 Architecture Building (1st floor)

  • Lecturer:

    Prof. Dr.-Ing. Dr. h.c. Jürgen Becker

  • SWS: 3
  • Lv-no.: 2311619
  • Information:

    Presence

Lecture languageEnglish
Organizational information

Please inform yourself about the current event dates in the Ilias.

Hardware synthesis and optimization

Recommendations

Basic knowledge of digital circuits, such as that taught in the course "Digital Technology" (2311615), is required.

Aims

Students know the basic steps required for the automated design of optimized digital circuits, can classify them in the Y-chart and assess their complexity.

They will be able to name and explain the most important solution approaches for these design steps and evaluate them in terms of optimality and computational effort. This includes the ability to apply the methods used within these approaches (e.g. selected graph algorithms or metaheuristics such as simulated annealing) and to determine their respective runtime complexities.

In addition, they can solve given problems from the field of design automation by selecting a suitable approach based on certain optimization criteria and applying it to the respective problem.


Contents

The module focuses on teaching the formal and methodological foundations for the automated design of optimized electronic systems. The relevant properties of the methods used from a scientific and methodological point of view are discussed, as well as their implementation in industrial practice.

The following topics are covered:

  • Graph algorithms and complexity
  • High-level synthesis
  • Register transfer level synthesis
  • Logic optimization
  • Technology mapping
  • Physical design

Exercises

The accompanying exercises are intended to consolidate the knowledge acquired in the lectures. Selected topics are repeated and students learn how to apply the methods for modern system design using theoretical and practical examples.