Next-Gen Hardware Generators for Safe AI Systems (Chisel)


Next-Gen Hardware Generators for Safe AI Systems (Chisel)

RISC-V-Logo in Blau und Gelb. riscv.org
Context

With the ever-increasing proportion of information technology in safety-critical applications such as autonomous driving, industrial automation and medical technology, the need to reduce development times for safe and reliable chips is also growing.

In addition to proven hardware development languages such as VHDL or Verilog, more modern languages such as Chisel have emerged in recent years, with the application focus being on the development of hardware generators. These can generate different configurations of similar modules by adjusting individual parameters without additional development effort.

Tasks

Your tasks as a HiWi include:

  • Researching open-source RiscV cores and Chisel AI accelerators
  • Extension of various hardware modules with different security mechanisms (e.g. error-correcting code or redundancy)
  • Chisel design of hardware generators for the IP blocks extended by security mechanisms.
Requirements
  • Basics in hardware design and digital circuits, basic knowledge of any hardware description language
  • Interest in learning and working with Chisel
  • Interest in the development of secure embedded systems