Digital Hardware Design Laboratory

Language of instructionEnglish
Organisational issues

Di 14:00-18:00 ITIV Geb. 30.10, Raum 216

Praktikum Entwurf digitaler Systeme (PES)/ Digital Hardware Design Laboratory (DHL)

Recommendations

Fundamentals of Electronic Systems Design (e.g. SAE, course code 23606, HSO, course code 23619 and HMS, course code 23608).

Contents

Modern technologies like artificial intelligence or image processing for autonomous driving require more and more computing power. There is a clear trend towards tailored computer chips and architectures. For this reason, the ability to design and create them is a very important skill for engineers nowadays. In the Digital Hardware Design Laboratory (DHL) you have the chance to learn and apply these skills.

The lab is part of the TivSeg laboratory projects at ITIV. The objective is to build an image processing chain that is able to interpret camera data and helps to control the movement of the Segway. Therefore, we use the FPGA-logic of the TivSeg.

In this laboratory, students practically apply development and simulation techniques known from the lectures. In DHL, students use the development and synthesis tools from Xilinx as well as the simulation tool ModelSim from Mentor Graphics, which are both widely-used in the industry. The sources developed in the laboratory are tested on an industrial grade hardware platform.

The target platform of the laboratory is the Digilent ZEDBOARD, which is equipped with a Xilinx Zynq System-on-Chip (SoC). The Zynq combines FPGA logic modules with a dual core ARM processor on a single chip.
In the first part of the laboratory (four sessions), you learn the fundamentals of the synthesis and simulation tools as well as the hardware description language Very High Speed Integrated Circuit Hardware Description Language (VHDL). First, you learn about the basic components of a FPGA and how you can program it. Subsequently, basic knowledge on the creation of testbenches is imparted. At the end of the introduction phase, you are able to implement common patters such as Finite State Machines (FSM) as well as complex circuits like dividers or interfaces.

Afterwards the actual project-part of the laboratory starts. Here you develop a hardware accelerator for camera image processing using the Zynq FPGA module. Based on the raw camera data the accelerator is able to identify prominent areas (regions) and transmits the results back to the processor. The processor can now control the TivSeg system based on this information or visualize the detected regions on a monitor connected to the HDMI interface of the ZEDBOARD.