Hardware-Synthese und -Optimierung

  • type: Vorlesung (V)
  • chair: KIT-Fakultäten - KIT-Fakultät für Elektrotechnik und Informationstechnik - Institut für Technik der Informationsverarbeitung
  • semester: SS 2021
  • time:

    Mondays
    12:00 - 13:30

    Tuesdays
    10:00 - 11:30

    Practice (LV-No. 2311621)

  • lecturer:

    Prof. Dr.-Ing. Dr. h. c. Jürgen Becker

  • sws: 3
  • lv-no.: 2311619
  • information: Online
VortragsspracheDeutsch

Hardware-Synthese und -Optimierung

Recommendations

Basic knowledge of digital circuits as it is conveyed in the lecture “Digitaltechnik” (2311615) is required.

 

Targets

The students know the basic steps involved in the automated design of optimized digital circuits, are able to locate them in the Y diagram, and to evaluate their complexity.

They are able to name the most important approaches to solve these steps, to describe them, and to evaluate them most importantly with respect to their optimality and their computational effort. This comprises the ability to apply methods that are part of these approaches (as for instance selected graph algorithms or metaheuristics such as Simulated Annealing) and to evaluate their respective time complexities.

Furthermore, they are able to solve a given problem from the field of design automation by choosing a suitable approach based on certain optimization criteria and applying it to the particular problem.

 

Content

The focus of this module lies on conveying formal and methodological principles for the automated design of optimized electronic systems. Scientifically and methodologically relevant properties of the approaches that are employed to do so are discussed, while their implementations in industrial environments are conveyed at the same time.

The following topic areas are considered:

  • Graph algorithms and complexity
  • High-level synthesis
  • Register-transfer-layer synthesis
  • Logic optimization
  • Technology mapping
  • Physical design