Hardware-Synthese und -Optimierung
- Type: Lecture (V)
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Chair:
KIT-Fakultäten - KIT-Fakultät für Elektrotechnik und Informationstechnik - Institut für Technik der Informationsverarbeitung
KIT-Fakultäten - KIT-Fakultät für Elektrotechnik und Informationstechnik - Semester: SS 2022
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Time:
Monday 17.04.2023
11:30 - 13:00
30.10 Raum 339
30.10 Nachrichtentechnik, Institutsgebäude (EG)
Mondays
11:30 - 13:00
30.33 Messtechnik-Hörsaal (MTI)
30.33 Allgemeine Elektrotechnik (EG)Tuesdays
09:45 - 11:15
30.10 Nachrichtentechnik-Hörsaal (NTI)
30.10 Nachrichtentechnik, Institutsgebäude (EG)Allocation lecture/practice: see schedule in ILIAS-course
- Lecturer:
- SWS: 3
- Lv-no.: 2311619
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Information:
On-Site
Please note: the first lecture on 17.04.2023 will take place in room 339 in the ITIV building 30.10.
Language of instruction | German |
Hardware-Synthese und -Optimierung
Recommendations
Basic knowledge of digital circuits as it is conveyed in the lecture “Digitaltechnik” (2311615) is required.
Targets
The students know the basic steps involved in the automated design of optimized digital circuits, are able to locate them in the Y diagram, and to evaluate their complexity.
They are able to name the most important approaches to solve these steps, to describe them, and to evaluate them most importantly with respect to their optimality and their computational effort. This comprises the ability to apply methods that are part of these approaches (as for instance selected graph algorithms or metaheuristics such as Simulated Annealing) and to evaluate their respective time complexities.
Furthermore, they are able to solve a given problem from the field of design automation by choosing a suitable approach based on certain optimization criteria and applying it to the particular problem.
Content
The focus of this module lies on conveying formal and methodological principles for the automated design of optimized electronic systems. Scientifically and methodologically relevant properties of the approaches that are employed to do so are discussed, while their implementations in industrial environments are conveyed at the same time.
The following topic areas are considered:
- Graph algorithms and complexity
- High-level synthesis
- Register-transfer-layer synthesis
- Logic optimization
- Technology mapping
- Physical design