english | Home | Impressum | KIT
Becker

Prof. Dr.-Ing. Jürgen Becker

Institutsleiter
Raum: 324
Tel.: +49 721 608-42502
Fax: +49 721 608-42511
beckerKuo0∂kit edu
Engesserstr. 5

76131 Karlsruhe


Prof. Dr.-Ing. Jürgen Becker

Lebenslauf

Studium der Informatik an der Universität Kaiserslautern (Vertiefung Technische Informatik), Abschluss 1992 mit dem Diplom. Von 1992 bis 1997 Wissenschaftlicher Mitarbeiter am Lehrstuhl für Rechnerstrukturen mit Forschungsinteressen in Rechnerarchitekturen (rekonfigurierbare Akzeleratoren), Hardware/Software Codesign und parallelisierenden Compilern, Administrator des europäischen Entwurfsprojekts EUROCHIP an der Universität Kaiserslautern. Abschluss in 1997 mit der Promotion (Dr.-Ing.). Von 1997 bis 2001 Wissenschaftlicher Assistent im Fachbereich Elektrotechnik und Informationstechnik (Lehrstuhl Mikroelektronische Systeme) an der TU Darmstadt. In der Lehre wurden High-Level Synthese und VLSI CAD Algorithmen vertreten, in der industrienahen Forschung Schwerpunkte in dynamisch rekonfigurierbaren Systems-on-Chip und IP-basierten Anwendungsabbildungsverfahren bearbeitet.

2001 Ruf an die Universität Karlsruhe (TH), Institutsleitung des Instituts für Technik der Informationsverarbeitung (ITIV) in der Fakultät für Elektrotechnik und Informationstechnik, Direktor der Gruppe Embedded Systems and Sensors Engineering (ESS) des Forschungszentrum Informatik (FZI) und von 2001 bis 2005 Stellvertretender Direktor (geschäftsführend) des International Department an der Universität Karlsruhe (TH). Landeslehrpreisträger Baden-Württemberg 2003.

Autor und Coautor von mehr als 250 Veröffentlichungen mit Schwerpunkt Architekturen und Entwurf von Eingebetteten Elektronischen Systemen mit vielfältigen u.a. industriellen Projekten, insbesondere im Bereich Automotive. Aktiv als Tagungsleiter und in zahlreichen Programmausschüssen internationaler Konferenzen und Workshops, Mitglied der GI und Senior Member des IEEE, Sprecher der GI/ITG-Fachgruppe Architekturen für hochintegrierte Schaltungen. Außerdem Mitarbeit im Editorial Board of IEEE Transaction on Computers und Executive Committee der Deutschen Sektion des IEEE. Professor Becker war von Oktober 2005 als Prorektor der Universität Karlsruhe (TH), bzw. von Oktober 2009 bis März 2012 als Chief Higher Education Officer (CHEO) des KIT zuständig für den Bereich Studium und Lehre. Prof. Becker ist seit 01.07.2012 CLUSTER Generalsekretär (Consortium aus 12 Universitäten).

 

Forschung

Leitung des Forschungsbereichs „Eingebettete elektronische Systeme“ mit den Forschungsprojekten

  • Systementwurf für rekonfigurierbare Hardware im Automobil
  • IP-basierter Mikroelektronikentwurf für Mobilfunksysteme
  • Hardware/Software Codesign und Architektursynthese
  • Hardware-Synthese und System-on-Chip-Integration

 

Lehre

 

Aktivitäten

 



45 Veröffentlichungen im Jahr 2012


  • M. Ferger, M. Al Kadi, M. Huebner, M. Koedam, S. Sinha, K. Goossens, G. M. Almeida, J. R. Azambuja, J. Becker
    Hardware / Software Virtualization for the Reconfigurable Multicore Platform (Link)
    In Computational Science and Engineering (CSE), 2012 IEEE 15th International Conference on, S. 341-344, 2012

  • J. Becker, T. Stripf, O. Oey, M. Huebner, S. Derrien, D. Menard, O. Sentieys, G. Rauwerda, K. Sunesen, N. Kavvadias, K. Masselos, G. Goulas, P. Alefragis, N. S. Voros, D. Kritharidis, N. Mitas, D. Goehringer
    From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach (Link)
    In Digital System Design (DSD), 2012 15th Euromicro Conference on, S. 114-121, 2012

  • T. Stripf, O. Oey, T. Bruckschloegl, R. Koenig, J. Becker, G. Goulas, P. Alefragis, N. S. Voros, J. Potman, K. Sunesen, S. Derrien, O. Sentieys
    A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems (Link)
    In Computational Science and Engineering (CSE), 2012 IEEE 15th International Conference on, S. 383-390, 2012

  • G. Goulas, P. Alefragis, N. S. Voros, C. Valouxis, C. Gogos, N. Kavvadias, G. Dimitroulakos, K. Masselos, D. Goehringer, S. Derrien, D. Menard, O. Sentieys, M. Huebner, T. Stripf, O. Oey, J. Becker, G. Rauwerda, K. Sunesen, D. Kritharidis, N. Mitas
    From Scilab to multicore embedded systems: Algorithms and methodologies (Link)
    In Embedded Computer Systems (SAMOS), 2012 International Conference on, S. 268-275, 2012

  • J. Heisswolf, R. Koenig, J. Becker
    A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling (Link)
    In Parallel and Distributed Processing with Applications (ISPA), 2012 IEEE 10th International Symposium on, S. 625-632, 2012

  • K. Siozos, H. Sidiropoulos, D. Diamantopoulos, P. Figuli, D. Soudris, M. Huebner, J. Becker
    On Designing Self-Aware Reconfigurable Platforms
    In Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012

  • R. Schmogrow, M. Meyer, S. Wolf, B. Nebendahl, D. Hillerkuss, B. Baeuerle, M. Dreschmann, J. Meyer, M. Huebner, J. Becker, C. Koos, W. Freude, J. Leuthold
    150 Gbit/s Real-Time Nyquist Pulse Transmission Over 150 km SSMF Enhanced by DSP with Dynamic Precision (Link)
    In Optical Fiber Communication Conference, S. OM2A.6, 2012

  • J. Becker, O. Sander, C. Roth
    Processor Solutions for Smart Mobility (Link)
    In 48. Workshop der Multi Projekt Chip - Gruppe der Hochschulen in Baden-Württemberg / Deutschland, 2012

  • M. Birk, M. Balzer, N. Ruiter, J. Becker
    Comparison of processing performance and architectural efficiency metrics for FPGAs and GPUs in 3D Ultrasound Computer Tomography (Link)
    In Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on, S. 1 -7, 2012

  • M. Ferger, A. Kadi, M. Koedam, M. Huebner, S. Sinha, K. Goossens, G. Almeida, J. R. Azambuja, J. Becker
    Hardware/Software Virtualization for the Reconfigurable Multicore Platform
    In Int'l Conference on Embedded and Ubiquitous Computing (EUC), 2012

  • O. Oey, S. Werner, D. Goehringer, A. Stuckert, J. Becker, M. Huebner
    Virtualization of heterogeneous and adaptive multi-core/multi-board systems (Link)
    In Design and Architectures for Signal and Image Processing (DASIP), 2012 Conference on, S. 1 -2, 2012

  • S. Ayhan, V. Vu-Duy, P. Pahl, S. Scherr, M. Huebner, J. Becker, T. Zwick
    FPGA controlled DDS based frequency sweep generation of high linearity for FMCW radar systems (Link)
    In Microwave Conference (GeMiC), 2012 The 7th German, S. 1 -4, 2012

  • C. Schmutzler, M. Simons, J. Becker
    On demand dependent deactivation of automotive ECUs
    In Design, Automation Test in Europe Conference Exhibition (DATE), 2012, S. 69 -74, 2012

  • F. Mendoza, J. Pascal, P. Nenninger, J. Becker
    Framework for dynamic verification of multi-domain virtual platforms in industrial automation (Link)
    In Industrial Informatics (INDIN), 2012 10th IEEE International Conference on, S. 935 -940, 2012

  • J. R. Azambuja, S. Pagliarini, M. Altieri, F. L. Kastensmidt, M. Huebner, J. Becker, G. Foucard, R. Velazco
    A Fault Tolerant Approach to Detect Transient Faults in Microprocessors Based on a Non-Intrusive Reconfigurable Hardware (Link)
    In Nuclear Science, IEEE Transactions on, Band 59, S. 1117 -1124, 2012

  • J. Heisswolf, A. Zaib, A. Weichslgartner, R. Koenig, T. Wild, J. Teich, A. Herkersdorf, J. Becker
    Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS (Link)
    In Parallel and Distributed Processing Symposium Workshops PhD Forum (IPDPSW), 2012 IEEE 26th International, S. 234 -241, 2012

  • W. Freude, R. Schmogrow, B. Nebendahl, M. Winter, A. Josten, D. Hillerkuss, S. Koenig, J. Meyer, M. Dreschmann, M. Huebner, C. Koos, J. Becker, J. Leuthold
    Quality metrics for optical signals: Eye diagram, Q-factor, OSNR, EVM and BER (Link)
    In Transparent Optical Networks (ICTON), 2012 14th International Conference on, S. 1 -4, 2012

  • D. Goehringer, L. Meder, S. Werner, O. Oey, J. Becker, M. Huebner
    Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration (Link)
    In International Journal of Reconfigurable Computing, Band 2012, S. 14, 2012

  • M. Niknahad, O. Sander, J. Becker
    Fine grain fault tolerance - A key to high reliability for FPGAs in space (Link)
    In Aerospace Conference, 2012 IEEE, S. 1 -10, 2012

  • G. Corradi, R. Girardey, J. Becker
    Xilinx tools facilitate development of FPGA applications for IEC61508 (Link)
    In Adaptive Hardware and Systems (AHS), 2012 NASA/ESA Conference on, S. 54 -61, 2012

  • C. Tradowsky, E. Cordero, T. Deuser, M. Huebner, J. Becker
    Determination of On-Chip Temperature Gradients on Reconfigurable Hardware (Link)
    In Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on, S. 1-8, 2012

  • D. Hillerkuss, R. Schmogrow, M. Meyer, S. Wolf, M. Jordan, P. Kleinow, N. Lindenmann, P. Schindler, A. Melikyan, X. Yang, S. Ben Ezra, B. Nebendahl, M. Dreschmann, J. Meyer, F. Parmigiani, P. Petropoulos, B. Resan, A. Oehler, K. Weingarten, L. Altenhain, T. Ellermeyer, M. Moeller, M. Huebner, J. Becker, C. Koos, W. Freude, J. Leuthold
    Single-Laser 32.5 Tbit/s Nyquist WDM Transmission (Link)
    In J. Opt. Commun. Netw., Band 4, S. 715--723, 2012

  • W. Freude, R. Schmogrow, D. Hillerkuss, J. Meyer, M. Dreschmann, B. Nebendahl, M. Huebner, J. Becker, C. Koos, J. Leuthold
    Reconfigurable optical transmitters and receivers (Link)
    In SPIE Proceedings, Band "8284", S. 82840A-82840A-8, 2012

  • M. Birk, R. Dapp, M. Balzer, N. Ruiter, J. Becker
    GPU-accelerated Transmission Tomography in 3D Ultrasound Computer Tomography
    In 2012 Workshop on Tomography, data processing and image reconstruction for medicine and engineering, 10. - 12.09.2012, Dresden, Germany, 2012

  • M. Birk, M. Zapf, M. Balzer, N. Ruiter, J. Becker
    A comprehensive comparison of GPU- and FPGA-based acceleration of reflection image reconstruction for 3D ultrasound computer tomography (Link)
    In Journal of Real-Time Image Processing, 2012

  • T. Stripf, O. Oey, T. Bruckschloegl, R. Koenig, M. Huebner, G. Goulas, P. Alefragis, N. S. Voros, G. Rauwerda, K. Sunesen, S. Derrien, D. Menard, O. Sentieys, N. Kavvadias, G. Dimitroulakos, K. Masselos, D. Goehringer, T. Perschke, D. Kritharidis, N. Mitas, J. Becker
    A Flexible Approach for Compiling Scilab to Reconfigurable Multi-Core Embedded Systems (Link)
    In 2012 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip {(ReCoSoC)}, 2012

  • F. Lemmonier, P. Millet, G. Almeida, M. Huebner, J. Becker, S. Pillement, O. Sentieys, M. Koedam, S. Sinha, K. Goossens, C. Piguet, M. Morgan, R. Lemaire
    Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures
    In International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'2012), 2012

  • C. Roth, J. Meyer, M. Rueckauer, O. Sander, J. Becker
    Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels
    In Hindawi International Journal of Reconfigurable Computing, Special Issue: Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011), 2012

  • O. Sander, C. Roth, B. Glas, J. Becker
    Towards Design and Integration of a Vehicle-to-X based Adaptive Cruise Control
    In FISITA 2012 World Automotive Congress, 2012

  • C. Roth, S. Reder, G. Erdogan, O. Sander, G. Almeida, H. Bucher, J. Becker
    Asynchronous Parallel MPSoC Simulation on the Single-chip Cloud Computer
    In International Symposium on System-on-Chip, Tampere, Finland, 2012

  • S. Werner, O. Oey, D. Goehringer, M. Huebner, J. Becker
    Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems
    In Design, Automation Test in Europe Conference Exhibition (DATE), 2012, S. 280 -283, 2012

  • J. Meyer, S. Menzel, M. Dreschmann, R. Schmogrow, D. Hillerkuss, W. Freude, J. Leuthold, J. Becker
    Ultra high speed digital down converter design for Virtex-6 FPGAs
    In 17th International OFDM Workshop 2012 (InOWo'12), 2012

  • M. Huebner, D. Goehringer, C. Tradowsky, J. Henkel, J. Becker
    Adaptive processor architecture - invited paper (Link)
    In Embedded Computer Systems (SAMOS), 2012 International Conference on, S. 244-251, 2012

  • T. Stripf, R. Koenig, J. Becker
    A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files
    In Parallel Distributed Processing, Workshops and Phd Forum (IPDPSW), 2012 IEEE International Symposium on, 2012

  • T. Stripf, R. Koenig, J. Becker
    A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture
    In Design, Automation Test in Europe Conference Exhibition (DATE), 2012, S. 21 -26, 2012

  • C. Tradowsky, F. Thoma, M. Huebner, J. Becker
    LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture (Best Work-in-Progress (WiP) Paper Award) (Link)
    In Industrial Embedded Systems (SIES), 2012 7th IEEE International Symposium on, S. 279-282, 2012

  • C. Tradowsky, F. Thoma, M. Huebner, J. Becker
    On Dynamic Run-Time Processor Pipeline Reconfiguration (Link)
    In Parallel and Distributed Processing Symposium Workshops PhD Forum (IPDPSW), 2012 IEEE 26th International, S. 419-424, 2012

  • M. Rueckauer, J. Meyer, T. Schubert, M. Huebner, D. Scheurer, J. Becker
    Realtime PCI Express Monitoring for Self Adaptive Reconfigurable Systems
    In International Multi-Conference on Systems, Signals and Devices 2012 (SSD '12), 2012

  • N. Dahm, M. Huebner, J. Becker
    FPGA System-on-Chip Solution for a Field Oriented Hybrid Stepper Motor Control
    In SSD-SAC proceedings, S. 6, 2012

  • N. Dahm, M. Hagner, M. Huebner, J. Becker
    FPGA based System-on-Chip Solution for Compensation of aging Motor Parameters of two Phase Hybrid Stepper Motors
    In embedded world conference proceedings, S. 10, 2012

  • J. Becker, S. Friederich, J. Heisswolf, R. Koenig, D. May
    Hardware Prototyping of Novel Invasive Multicore Architectures
    In Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), S. 201--206, 2012

  • C. Roth, S. Reder, O. Sander, M. Huebner, J. Becker
    A Framework for Exploration of Parallel SystemC Simulation on the Single-chip Cloud Computer
    In 5th International ICST Conference on Simulation Tools and Techniques, Desenzano, Italy, 2012

  • R. Schmogrow, M. Winter, M. Meyer, D. Hillerkuss, S. Wolf, B. Baeuerle, A. Ludwig, B. Nebendahl, S. Ben Ezra, J. Meyer, M. Dreschmann, M. Huebner, J. Becker, C. Koos, W. Freude, J. Leuthold
    Real-time Nyquist pulse generation beyond 100 Gbit/s and its relation to OFDM (Link)
    In Opt. Express, Band 20, S. 317--337, 2012

  • M. Dreschmann, J. Meyer, M. Huebner, R. Schmogrow, D. Hillerkuss, J. Becker, J. Leuthold, W. Freude
    Time And Frequency Synchronization For Ultra-High Speed OFDM Systems
    In International Conference on Computing, Networking and Communications (ICNC), 2012

  • R. Schmogrow, B. Nebendahl, M. Winter, A. Josten, D. Hillerkuss, S. Koenig, J. Meyer, M. Dreschmann, M. Huebner, C. Koos, J. Becker, W. Freude, J. Leuthold
    Error Vector Magnitude as a Performance Measure for Advanced Modulation Formats (Link)
    In Photonics Technology Letters, IEEE, Band PP, S. 61-63, 2012

Veröffentlichungen nach Jahren auflisten
Aktuelle 2013 2012 2011 2010 2009 2008 2007 2006 2005 2004 2003 2002 2001 2000 1999 1998 1997 1996 1995