Key topics of his dissertation
Fabian has focused his research on adaptive computer architectures. In doing so, he has developed a concept that allows computers for high-performance applications—such as those used in autonomous driving—to be both efficient (i.e., with low power dissipation) and flexible (for different types of algorithms). Flexibility is important in the automotive sector so that vehicles can be updated retroactively and the algorithms improved—for example, to enhance driving functions. At the same time, however, efficiency is also extremely important to ensure that range is not significantly compromised and that no unnecessary additional emissions are generated. The architectures he investigated were made more flexible through the strategic placement of embedded FPGA units, without compromising efficiency.
🎉 After the defense, Fabian’s team members surprised him—as is tradition—with a custom-designed doctoral cap—handcrafted after work and filled with loving details from his field of research. The ITIV has upheld this tradition for many years, creating special moments every time.
The entire institute extends its warmest congratulations and shares in Fabian’s joy over this tremendous success!
Design of Heterogeneous Manycore Platforms
As performance requirements for integrated circuits continue to rise, the semiconductor industry is struggling to keep pace with these demands. Issues with power density and static leakage have come to the forefront, while earlier phenomena such as Dennard scaling have ceased to apply. To gain additional performance, the number of processor cores is being increased instead. Such many-core systems with hundreds of processors require a different hardware design than traditional embedded systems. The programmability of such systems also differs significantly, as problems must be highly parallelized.
Runtime-Adaptive Architectures
A modern system-on-chip must conserve chip area and power to enable the design of small, mobile devices with long battery life. Nevertheless, users expect very high computing power for very specific tasks, such as media processing or neural network inference. By developing hardware architectures that can be reconfigured at runtime, they become more versatile and even future-proof for use cases that are not yet known at the time of development—while reducing chip area and minimizing the “dark silicon” effect. When developing such adaptive hardware architectures, various design parameters must be carefully balanced to ensure that the system is suitable for as many purposes as possible.
Hypervisor-Based Systems for Safety-Critical Applications
Safety-critical applications are found particularly in the vehicle and plant control and regulation division. Such systems are complex to develop and maintain, as flawless functionality must be guaranteed—even after an update. By utilizing modern virtualization technologies, the isolation of individual system components can be improved. This increases the complexity of the overall system and makes safety assessments more challenging. The target of this research is to reduce the barriers to using a hypervisor in these divisions.
Student Projects I Have Supervised (Selection)
- MA: "Distributed Real-Time Monitoring of Manycores"
- MA: "Design of a Processor-Based Near-Memory Accelerator"
- MA: "Development of a Dynamic and Flexible Memory Controller for Manycore Prototypes"
- MA: "Channel Estimation of Dynamic Intra-Tile Reallocatable Cache in Homogeneous GPPs"
- MA: "Hypervisor-Based Guest Monitoring in Safety-Critical Systems"
- MA: "Implementing an AI Accelerator as a Special Instruction"
- BA: "ARM Debugger for the Xen Hypervisor"
- BA: "Implementation of an Approximate Accelerator"
- BA: "Dynamic CNN Acceleration for the i-Core Processor"
Publications
Lesniak, F.
2026, September 21. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000196956
Gutermann, A.; Serdyuk, A.; Paraskevas, F.; Toto Kiesa, H.; Lesniak, F.; Schwarz, J.; Hartmann, M.; Harbaum, T.; Becker, J.
2026. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 98 (2), Art.Nr: 42. doi:10.1007/s11265-026-02012-w
Gutermann, A.; Serdyuk, A.; Lesniak, F.; Hoefer, J.; Toto Kiesa, H.; Harbaum, T.; Becker, J.; Pachideh, B.; Nitzsche, S.; Neher, M.; Weigelt, C.; Krausse, J.; Pazmino, V.; Knobloch, K.; Groth, L.; Nešković, A.; Mulhem, S.; Berekovic, M.
2026. 2026 Design, Automation & Test in Europe Conference (DATE), 1–7, Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/DATE69613.2026.11539165
Gutermann, A.; Serdyuk, A.; Paraskevas, F.; Toto Kiesa, H.; Lesniak, F.; Schwarz, J.; Hartmann, M.; Harbaum, T.; Becker, J.
2025. 2025 IEEE Nordic Circuits and Systems Conference, NorCAS 2025, Riga, 28th-29th October 2025, 1–7, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/NorCAS66540.2025.11231285
Stammler, M.; Lesniak, F.; Kumar, N. S.; Easwaran, A.; Becker, J.
2025. 2025 IEEE 38th International System-on-Chip Conference (SOCC), Dubai, 29th September 2025 - 1st October 2025, 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC66126.2025.11235395
Hoefer, J.; Lesniak, F. M.; Gutermann, A.; Wöran, F.; Harbaum, T.; Becker, J. E.
2025. 2025 IEEE 38th International System-on-Chip Conference (SOCC), Dubai, 29th September 2025 - 1st October 2025, 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC66126.2025.11235419
Karle, C.; Fuerst-Walter, I.; Schade, F.; Hoefer, J.; Lesniak, F.; Harbaum, T.; Becker, J.
2025. 2025 IEEE 4th German Education Conference (GECon), Hamburg, 21st-23rd July 2025, 1–5, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/GECon64629.2025.11369364
Lesniak, F.; Gutermann, A.; Harbaum, T.; Becker, J.
2024. GLSVLSI ’24: Proceedings of the Great Lakes Symposium on VLSI 2024, 151 – 157, Association for Computing Machinery (ACM). doi:10.1145/3649476.3658737
Lesniak, F.; Harbaum, T.; Becker, J.
2024. 2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapur, 18th - 21st December 2023, 340–346, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MCSoC60832.2023.00057
Anantharajaiah, N.; Lesniak, F.; Harbaum, T.; Becker, J.
2023. 2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 38 – 44, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MCSoC60832.2023.00014
Lesniak, F.; Harbaum, T.; Becker, J.
2023. 2023 IEEE 36th International System-on-Chip Conference (SOCC), Santa Clara, USA, 05-08 September 2023, 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC58585.2023.10257090
Anantharajaiah, N.; Xu, Y.; Lesniak, F.; Harbaum, T.; Becker, J.
2023. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISVLSI59464.2023.10238569
Lesniak, F.; Anantharajaiah, N.; Harbaum, T.; Becker, J.
2023. RAPIDO ’23: Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems, 31–38, Association for Computing Machinery (ACM). doi:10.1145/3579170.3579262
Guissouma, H.; Hohl, C. P.; Lesniak, F.; Schindewolf, M.; Becker, J.; Sax, E.
2022. IEEE Access, 10, 57696–57717. doi:10.1109/ACCESS.2022.3176879
Masing, L.; Lesniak, F.; Becker, J.
2021. IEEE embedded systems letters, 13 (1). doi:10.1109/LES.2020.2995084
Lesniak, F.; Kreß, F.; Becker, J.
2021. Applied Reconfigurable Computing. Ed.: S. Derrien, 221–231, Springer Nature Switzerland. doi:10.1007/978-3-030-79025-7_15
Anantharajaiah, N.; Kempf, F.; Masing, L.; Lesniak, F. M.; Becker, J.
2019. Proceedings of the 12th International Workshop on Network on Chip Architectures (NoCArc 2019), Columbus, OH, Ocober 12-13, 2019, 1–6, Association for Computing Machinery (ACM). doi:10.1145/3356045.3360718
Masing, L.; Lesniak, F.; Becker, J.
2019. 15th International Symposium on Applied Reconfigurable Computing, ARC 2019; Darmstadt; Germany; 9 April 2019 through 11 April 2019, 319–333. doi:10.1007/978-3-030-17227-5_23
Werner, S.; Masing, L.; Lesniak, F.; Becker, J.
2015. 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, United Kingdom, 2–4 September 2015, Art.Nr. 7294020, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/FPL.2015.7294020