Fabian Kreß, M. Sc.

Fabian Kreß, M. Sc.

  • Engesserstr. 5

    76131 Karlsruhe

Research interests

Design Space Exploration for Embedded AI Applications

Today, applications such as object detection or classification in the field of autonomous driving are usually realized by using Artificial Intelligence (AI). In contrast to conventional algorithms, AI can often provide more precise and reliable results. However, AI-based applications usually require to process a huge amount of operations. In the context of embedded platforms, it is therefore important to investigate, how latency, data throughput and power consumption of the system can be optimized considering the constraints imposed by the application.

Emerging Non-Volatile Memory Technologies

In recent decades, novel Non-Volatile Memory technologies (NVMs), such as MRAM or ReRAM, have been introduced and developed further. Emerging NVMs in general consume less static power than SRAM or DRAM and require only a fraction of the area compared to an SRAM cell. Additionally, these technologies enable efficient In-Memory Computing to accelerate matrix-vector multiplications, for example. Therefore, NVMs offer the opportunity to rethink established memory hierarchies and computer architectures for future systems.

Embedded FPGA Architecture and Toolchain

Embedded FPGAs (eFPGA) add flexibility to the entire system by allowing hardware reconfiguration during runtime. Hence, various workloads can be accelerated and the hardware accelerators themselves can also be updated. However, the initial layout of the eFPGA has to be defined before tape-out. This involves not only determining the number of LUTs but also the design of application-specific IPs. The integration of an eFPGA thus increases the complexity in the design phase which requires improved toolchains.

Teaching

Supervised student works (selection)

  • SA: “Emerging Memory Technologies and their use in new System Architectures”

Publications


2022
Conference Papers
Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs
Hotfilter, T.; Kreß, F.; Kempf, F.; Becker, J.; Haro, J. M. De; Jiménez-González, D.; Moretó, M.; Álvarez, C.; Labarta, J.; Baili, I.
2022. 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 14-23 March 2022, 628–631, Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/DATE54114.2022.9774716
2021
Conference Papers
FLECSim-SoC: A Flexible End-to-End Co-Design Simulation Framework for System on Chips
Hotfilter, T.; Hoefer, J.; Kreß, F.; Kempf, F.; Becker, J.
2021. IEEE 34th International System-on-Chip Conference (SOCC), 14th-17th September 2021, Las Vegas, Nevada, USA, 83–88, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC52499.2021.9739212
Transparent Near-Memory Computing with a Reconfigurable Processor
Lesniak, F.; Kreß, F.; Becker, J.
2021. Applied Reconfigurable Computing. Ed.: S. Derrien, 221–231, Springer Nature Switzerland AG. doi:10.1007/978-3-030-79025-7_15
2018
Conference Papers
In-NoC Circuits for Low-Latency Cache Coherence in Distributed Shared-Memory Architectures
Masing, L.; Srivatsa, A.; Kreß, F.; Anantharajaiah, N.; Herkersdorf, A.; Becker, J.
2018. IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Hanoi, VN, September 12-14, 2018, 138–145, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MCSoC2018.2018.00033
Presentations
In-NoC circuits for low-latency cache coherence in distributed shared-memory architectures
Masing, L.; Srivatsa, A.; Kreß, F.; Anantharajaiah, N.; Herkersdorf, A.; Becker, J.
2018. 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2018), Hanoi, Vietnam, September 12–14, 2018