Anantharajaiah Nidhi, M. Sc.

Anantharajaiah Nidhi, M. Sc.

  • Engesserstr. 5

    76131 Karlsruhe

Research interests

Adaptive Networks-on-Chip for Mixed-Criticality Systems

Multiple applications of different criticality are increasingly being executed on the same System-on-Chip (SoC) platform to reduce resource consumption. These platforms are moving towards multi/many core architectures and can use Networks-on-Chip (NoC) for communication. With the increasing number of cores on such platforms, the complexity of the interconnect is increasing and it will become a limiting factor for performance.  Performance on such systems can be improved if the NoC is able to adapt at runtime to the requirements of different applications.

Routing algorithms for non-mesh based topologies in a Networks-on-Chip

Mesh topology is commonly implemented in Networks-on-Chip (NoC) due to its scalability, ease of implementation and uniform nature. With the increase in complexity of on-chip interconnects for large scale multi/many core systems, using the mesh topology can become inefficient due to high hop counts. Hierarchical and multilayered topologies, irregular topologies are being investigated to improve overall performance of the system. Routing in such NoCs can become challenging and investigations are conducted here into routing algorithms for regular and irregular topologies.

Supervised student works (selection)

Seminar: Eingebettete Systeme:

  • Seminar: "Introduction and Analysis of Methods for Adaptive Networks-on-Chip"
  • Seminar: "Quality of Service in Adaptive Networks-on-Chip"

Bachelor / Master thesis:

  • MA: "Design and Implementation of an ACO Based Router for Mixed Criticality NoCs"
  • MA: "Improving Quality of Service in Adaptive Networks-on-Chip for Mixed-Criticality System"
  • MA. “Performance Comparison between the SXP and PCI Express Protocol with a Refinement Approach of SXP with Security”
  • BA: "Design and Implementation of a Self-Adaptive NoC"


Conference Papers
Ant Colony Optimization Based NoCs for Flexible Spatial Isolation in Mixed Criticality Systems
Anantharajaiah, N.; Knopf, F.; Becker, J.
2021. Proceedings 34th IEEE International System-on-Chip Conference (SOCC): September 14–17, 2021, Virtual. Ed.: G. Qu, 248–253, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC52499.2021.9739596
Multi-layered NoCs with Adaptive Routing for Mixed Criticality Systems
Anantharajaiah, N.; Zhang, Z.; Becker, J.
2021. Applied Reconfigurable Computing. Ed.: S. Derrien, 125–139, Springer Nature Switzerland AG. doi:10.1007/978-3-030-79025-7_9
Conference Papers
A Study of the Impact of Formulation of Cost Function in Task Mapping Problem on NoCs
Barros, J. B. de; Anantharajaiah, N.; Ayala-Rincon, M.; Llanos, C. H.; Becker, J.
2020. 2020 IEEE Nordic Circuits and Systems Conference (NorCAS), 1–7, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/NorCAS51424.2020.9265134
Conference Papers
A Network on Chip Adapter for Real-Time and Safety-Critical Applications
Kempf, F.; Anantharajaiah, N.; Masing, L.; Becker, J.
2019. 32nd IEEE International System on Chip Conference, SOCC 2019; Singapore; Singapore; 3 September 2019 through 6 September 2019. Ed.: D. Zhao, 39–44, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC46988.2019.1570558594
Dynamic and scalable runtime block-based multicast routing for networks on chips
Anantharajaiah, N.; Kempf, F.; Masing, L.; Lesniak, F. M.; Becker, J.
2019. Proceedings of the 12th International Workshop on Network on Chip Architectures (NoCArc 2019), Columbus, OH, Ocober 12-13, 2019, 1–6, Association for Computing Machinery (ACM). doi:10.1145/3356045.3360718
Conference Papers
In-NoC Circuits for Low-Latency Cache Coherence in Distributed Shared-Memory Architectures
Masing, L.; Srivatsa, A.; Kreß, F.; Anantharajaiah, N.; Herkersdorf, A.; Becker, J.
2018. IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Hanoi, VN, September 12-14, 2018, 138–145, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MCSoC2018.2018.00033
In-NoC circuits for low-latency cache coherence in distributed shared-memory architectures
Masing, L.; Srivatsa, A.; Kreß, F.; Anantharajaiah, N.; Herkersdorf, A.; Becker, J.
2018. 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2018), Hanoi, Vietnam, September 12–14, 2018