Fabian Kempf, M.Sc.

  • Engesserstr. 5

    76131 Karlsruhe

Research interests

Runtime Adaptive Many-Core Architectures

Modern processors have to fulfill more and more conflicting requirements. Processors should not only become more and more powerful and efficient, but also more and more error-resistant. One solution to meet these conflicting requirements is adaptive processor architectures, which adapt to the requirements and the situation.  Through adaptivity at runtime, the best compromise between the requirements can be achieved during operation.

Fault tolerance mechanisms based on adaptive hardware redundancy

With the increasing automation of driving, the risk of electronic malfunctions in the vehicle leading to physical damage is rising. In this context, relevant components must therefore increasingly be designed in such a way that they reliably provide a defined minimum level of functionality despite such malfunctions. This requires the use of suitable fault tolerance mechanisms. We are researching the particularly cost-effective implementation of such mechanisms using adaptive hardware redundancy.

Reliable AI accelerators in safety-critical environments

The basis for autonomous driving and other safety-critical applications is reliable perception of the near environment using cameras, as well as radar and lidar sensors. Machine learning, e.g. Convolutional Neural Networks, provide the best results for object detection. The current challenge is to integrate these neural networks into embedded systems while ensuring reliability. In particular, random hardware faults in AI accelerators as well as the inability of neural networks to estimate their own uncertainty still prevent safety-critical deployment

Supervised student works (selection)

  • SA: “Fault Tolerance in Embedded Mixed Critical Systems”

  • BA: “Concept and implementation of a dynamic lockstep architecture for a LEON3 Many-Core System”

  • BA: “Concept and implementation of a cache-based fault-tolerant mechanism for the LEON3 processor”

  • MA: “Concept and Implementation of an adaptive cache architecture for a LEON3 Many-Core System”

  • MA: “Investigation of machine learning approaches for error detection in control flow based on bus snooping”

Publications


2021
Conference Papers
An Adaptive Lockstep Architecture for Mixed-Criticality Systems.
Kempf, F.; Hartmann, T.; Bähr, S.; Becker, J.
2021. 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI): 7-9 July 2021, Tampa, FL, USA, 7–12, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISVLSI51109.2021.00013
2020
Conference Papers
Embedded Image Processing the European Way: A new platform for the future automotive market.
Hotfilter, T.; Kempf, F.; Becker, J.; Reinhardt, D.; Baili, I.
2020. 6th IEEE World Forum on Internet of Things, WF-IoT 2020, New Orleans, United States, 2 - 16 June 2020, Art.Nr. 9221396, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/WF-IoT48130.2020.9221396
2019
Journal Articles
Worst-Case Execution-Time-Aware Parallelization of Model-Based Avionics Applications.
Reder, S.; Kempf, F.; Bucher, H.; Becker, J.; Alefragis, P.; Voros, N.; Skalistis, S.; Derrien, S.; Puaut, I.; Oey, O.; Stripf, T.; Ferdinand, C.; David, C.; Ulbig, P.; Mueller, D.; Durak, U.
2019. Journal of aerospace information systems, 16 (11), 521–533. doi:10.2514/1.I010749
Conference Papers
A Network on Chip Adapter for Real-Time and Safety-Critical Applications.
Kempf, F.; Anantharajaiah, N.; Masing, L.; Becker, J.
2019. 32nd IEEE International System on Chip Conference, SOCC 2019; Singapore; Singapore; 3 September 2019 through 6 September 2019. Ed.: D. Zhao, 39–44, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC46988.2019.1570558594
Dynamic and scalable runtime block-based multicast routing for networks on chips.
Anantharajaiah, N.; Kempf, F.; Masing, L.; Lesniak, F. M.; Becker, J.
2019. Proceedings of the 12th International Workshop on Network on Chip Architectures (NoCArc 2019), Columbus, OH, Ocober 12-13, 2019, 1–6, Association for Computing Machinery (ACM). doi:10.1145/3356045.3360718
2018
Conference Papers
Data Reduction and Readout Triggering in Particle Physics Experiments Using Neural Networks on FPGAs.
Baehr, S.; Kempf, F.; Becker, J.
2018. Proceedings of the 18th International Conference on Nanotechnology (IEEE-NANO 2018), Cork, IRL, July 23-26, 2018, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/NANO.2018.8626239
Data Readout Triggering for Phase 2 of the Belle II Particle Detector Experiment Based on Neural Networks.
Baehr, S.; Kempf, F.; Becker, J.
2018. Proceedings of the 31th IEEE International System-on-Chip Conference (SOCC), Arlington, VA, September 4-7, 2018, 174–179, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC.2018.8618563