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Anantharajaiah Nidhi, M. Sc.

Anantharajaiah Nidhi, M. Sc.

Wissenschaftliche Mitarbeiterin
Gruppe: Prof. Becker
Raum: 226.2
CS 30.10
Tel.: +49 721 608-47169
nidhiVqz3∂kit edu

 Engesserstr. 5

76131 Karlsruhe

M. Sc. Nidhi Anantharajaiah

Curriculum Vitae

 

  • Born in July, 1990
  • Bachelor of Engineering degree in Telecommunication Engineering at PES Institute of Technology, Bangalore, India (Autonomous College) (2008 – 2012)
    • Undergraduate Project Title: Investigations into Custom Reconfigurable Architectures for Intelligent Systems
  • Research Assistant at PES Centre for Intelligent Systems, PES Institute of Technology, Bangalore, India (2012 – 2014)
  • Master of Science degree in Embedded Systems at Eindhoven University of Technology, The Netherlands (2014 - 2016)
    • Master Graduation Project Title: Investigating time synchronization using IEEE 1588 on a heterogeneous multi-core platform
  • Wissenschaftliche Mitarbeiterin at ITIV from October, 2016

 

 

Teaching

Exercises for 2311616 Communication Systems and Protocols

Seminar: Embedded Systems (http://www.itiv.kit.edu/english/60_6071.php)

 

 

Supervised student work

Seminar: Eingebettete Systeme:

  • "Introduction and Analysis of Methods for Adaptive Networks-on-Chip"
  • "Quality of Service in Adaptive Networks-on-Chip"

Bachelor-/ Master thesis:

  • BA: "Design and Implementation of a Self-Adaptive NoC"
Studentische Arbeiten
Titel Datum
Investigating Adaptive Networks-on-Chip for Mixed-Criticality Systems offen (zu vergeben)


Publikationen


2019
Proceedingsbeiträge
Dynamic and scalable runtime block-based multicast routing for networks on chips.
Anantharajaiah, N.; Kempf, F.; Masing, L.; Lesniak, F. M.; Becker, J.
2019. Proceedings of the 12th International Workshop on Network on Chip Architectures (NoCArc 2019), Columbus, OH, Ocober 12-13, 2019, 1–6, ACM Press, New York, NY. doi:10.1145/3356045.3360718
2018
Proceedingsbeiträge
In-NoC Circuits for Low-Latency Cache Coherence in Distributed Shared-Memory Architectures.
Masing, L.; Srivatsa, A.; Kreß, F.; Anantharajaiah, N.; Herkersdorf, A.; Becker, J.
2018. IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Hanoi, VN, September 12-14, 2018, 138–145, IEEE. doi:10.1109/MCSoC2018.2018.00033
Vorträge
In-NoC circuits for low-latency cache coherence in distributed shared-memory architectures.
Masing, L.; Srivatsa, A.; Kreß, F.; Anantharajaiah, N.; Herkersdorf, A.; Becker, J.
2018. 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2018), Hanoi, Vietnam, 12.–14. September 2018