RIGOLETTO – RISC-V-Generation von leistungsstarken Automobilprozessoren und Rechenplattformen

Motivation

RISC-V open-source and open-standard approach enables flexible, productive platforms for a wide market access. RIGOLETTO will prepare the way for further exploiting the potential of RISC-V ISA (instruction set architecture) as a key technology to address the demands in the context of future Software Defined Vehicles, supporting powerful in-car computing and real-time processor architectures.

Project goals

The project goal is to expand and industrialize a European RISC-V automotive ecosystem for next-generation high-performance processors. RIGOLETTO will enable safe, secure, and real-time automotive functions on an open RISC-V ISA, laying the foundation for a next-generation Automotive Computing Platform. The project will develop a dedicated Automotive Processor Family with accelerators, emphasizing open-source solutions and EDA tools for processor and chip design.

ITIV involvement

One aspect that ITIV is working on is the design of accelerators for embedded and automotive AI applications by contributing to the full design-to-deployment toolchain. This includes an efficient accelerator, co-design algorithm and automated mapping of complex AI workloads. The accelerator will provide software interfaces for integration through dedicated instruction set extensions for the automotive RISC-V architecture.