Practical course Design of Digital Systems (PES)

Notes

Registration for the internship takes place online via the ILIAS portal of the KIT in the corresponding ILIAS course room (see ilias.studium.kit.edu). The registration will be activated on April 11, 2026.

The preliminary discussion will take place on Tuesday, April 21, 2026 at 2 p.m. in room 339 (Engesserstr. 5, building 30.10) of the Institute of Information Processing Technology (ITIV). The actual practical course will take place on Tuesdays from 14:00 to 18:00. If the number of participants is high, a second session may be offered on Mondays from 14:00 to 18:00.

The number of internship places is limited. Online registration does not guarantee participation in the internship. The final decision on participation and the allocation of dates can only be made in the preliminary meeting. Students for whom the internship is a compulsory subject have priority.

Recommendations:

Knowledge of the design and design automation of electronic systems (e.g. HSO, No. 2311619 or HMS, No. 2311608).

Content:

Modern technologies like artificial intelligence or image processing for autonomous driving require more and more computing power. There is a clear trend towards tailored computer chips and architectures. For this reason, the ability to design and create them is a very important skill for engineers nowadays. In the Digital Hardware Design Laboratory (DHL) you have the chance to learn and apply these skills.

In this laboratory, students practically apply development and simulation techniques known from the lectures. In DHL, students use the development and synthesis tools from Xilinx as well as the simulation tool ModelSim from Mentor Graphics, which are both widely-used in the industry. The sources developed in the laboratory are tested on an industrial grade hardware platform.

The target platform of the laboratory is the Digilent ZEDBOARD, which is equipped with a Xilinx Zynq System-on-Chip (SoC). The Zynq combines FPGA logic modules with a dual core ARM processor on a single chip.

In the first part of the laboratory (four sessions), you learn the fundamentals of the synthesis and simulation tools as well as the hardware description language VHDL. First, you learn about the basic components of a FPGA and how you can program it. Subsequently, basic knowledge on the creation of testbenches is imparted. At the end of the introduction phase, you are able to implement common patters such as Finite State Machines (FSM) as well as complex circuits like dividers or interfaces.

Afterwards the actual project-part of the laboratory starts. Here you develop a hardware accelerator for camera image processing using the Zynq FPGA module. Based on the raw camera data the accelerator is able to identify prominent areas (regions) and transmits the results back to the processor. The processor can now visualize the detected regions on a monitor connected to the HDMI interface of the ZEDBOARD.