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M. Tech. Shalina Figuli

Wissenschaftliche Mitarbeiterin
Gruppe: Prof. Becker
Raum: 218.2
Tel.: +49 721 608-48427
Fax: +49 721 608-42511
shalina fordUzc7∂kit edu

Engesserstr. 5

76131 Karlsruhe



M. Tech. Shalina Percy Delicia Figuli

Lebenslauf

  • Geboren im Oktober 1989
  • Studium der Elektrotechnik (VLSI Design) an der Karunya Universität, Coimbatore (Indien)
    • Bachelor Abschluss im Mai 2011
    • Thema der Bachelorarbeit: Retrofitting of Relay Logic Based Stud Welding Machine using Programmable Logic Controller
    • Masterabschluss im Mai 2013
    • Thema der Masterarbeit: Bringing Accuracy to Open Virtual Platforms (OVP): A Safari from High-Level Tools to Low-Level Microarchitectures
  • Am ITIV seit September 2013

 

 

Forschung

  • Architectures and tools for highly efficient system-on-chip
  • FPGA based highspeed communication systems
     
  • Fellow in the Helmholtz International Research School for Teratronics (HIRST)
    Terahertz technology has become a highly emerging research field, surfacing the known knowledge of the advancing world and making it to step into the unexploited gap called Terahertz gap, that lies in full potential, sandwiching itself between the microwave and infrared frequency ranges. This unharnessed gap has led to the birth of a new field called Teratronics which convolves within the key aspects of electronics and photonics. The continuously growing FPGA domain with the blooming parallelization, pipelining and reconfiguration facilities is aimed to make its mark in the future scientific world by bringing terahertz frequency application into reality. However, for now, advances in the context of Teratronics are mainly on fundamental physical layer, dealing with low complexity. There is a big gap to the application domain and the system level, because today's and near future FPGAs are not meeting the Terahertz demands. The Helmholtz International Research School for Teratronics (HIRST) endeavors to close this gap by developing and exploring future FPGA technologies by identifying their bottlenecks and incorporating latest promising breakthrough physical technologies such as optical on-chip interconnects.
     
  • Fellow in the Karlsruhe School of Elementary Particle and Astroparticle Physics
    The tremendous data volumes in particle detectors demand for transfer rates in the range of Tb/s. Realizing these data rates on serial data connections like fibre optics arise interesting research questions throughout the whole communication and processing chain. Not only the physical link needs to be capable of the demanded bandwidth, but also the digital signal and data processing, including higher order modulation techniques for efficient bandwidth utilization and efficient communication protocols. With respect to digital signal and data processing, today’s general purpose CPUs and DSPs cannot achieve these demands. Moreover specialized highly parallel hardware is needed, thus the employment of FPGAs, that provide a large scale of programmable logic and DSP resources as well as specialized high-speed I/Os, seems very promising.

 

Lehre

 

Studentische Arbeiten

M. Tech. Shalina Percy Delicia Figuli
Titel Datum


Publikationen


2018
Proceedingsbeiträge
Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems.
Pfau, J.; Figuli, S. P. D.; Bähr, S.; Becker, J.
2018. Applied Reconfigurable Computing - Architectures, Tools, and Applications, Proceedings of the 14th International Symposium, ARC 2018, Santorini, Greece, 2nd - 4th May 2018. Ed.: Nikolaos Voros, 615-626, Springer, Cham. doi:10.1007/978-3-319-78890-6_49
2017
Zeitschriftenaufsätze
A Generic Reconfigurable Mixed Time and Frequency Domain QAM Transmitter with Forward Error Correction.
Figuli, S.; Figuli, P.; Sonnino, A.; Becker, J.
2017. International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems, 6 (2), 80-88
Challenges in QCD matter physics –The scientific programme of the Compressed Baryonic Matter experiment at FAIR.
Ablyazimov, T.; Abuhoza, A.; Adak, R. P.; Adamczyk, M.; Agarwal, K.; Aggarwal, M. M.; Ahammed, Z.; Ahmad, F.; Ahmad, N.; Ahmad, S.; Akindinov, A.; Akishin, P.; Akishina, E.; Akishina, T.; Akishina, V.; Akram, A.; Al-Turany, M.; Alekseev, I.; Alexandrov, E.; Figuli, S. P. D.; u. a.
2017. The European physical journal / A, 53 (3), 60. doi:10.1140/epja/i2017-12248-y
Proceedingsbeiträge
A Reconfigurable High-speed Spiral FIR Filter Architecture.
Figuli, S. P. D.; Figuli, P.; Becker, J.
2017. Proceedings of the 40th International Conference on Telecommunications and Signal Processing, TSP 2017, Barcelona, Spain, 5th - 7th July 2017, 532-537, IEEE, Piscataway (NJ). doi:10.1109/TSP.2017.8076044
Parameter Sensitivity in Virtual FPGA Architectures.
Figuli, P.; Ding, W.; Figuli, S.; Siozios, K.; Soudris, D.; Becker, J.
2017. 13th International Symposium on Applied Reconfigurable Computing, ARC 2017; Delft; Netherlands; 3 April 2017 through 7 April 2017. Ed. : S. Wong, 141–153, Springer International Publishing, Cham. doi:10.1007/978-3-319-56258-2_13
2016
Proceedingsbeiträge
A variable FPGA based generic QAM transmitter with scalable mixed time and frequency domain signal processing.
Figuli, S. P. D.; Sonnino, A.; Figuli, P.; Becker, J.
2016. 2016 39th International Conference on Telecommunications and Signal Processing (TSP), Vienna, Austria, 27–29 June 2016. Ed.: N. Herencsar, 453-457, IEEE, Piscataway (NJ). doi:10.1109/TSP.2016.7760919
2015
Proceedingsbeiträge
TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools.
Siozios, K.; Figuli, P.; Sidiropoulos, H.; Tradowsky, C.; Diamantopoulos, D.; Maragos, K.; Delicia, S. P.; Soudris, D.; Becker, J.
2015. 11th International Symposium on Applied Reconfigurable Computing, ARC 2015; Bochum; Germany; 13 April 2015 through 17 April 2015. Ed.: K. Sano, 103–114, Springer International Publishing, Cham. doi:10.1007/978-3-319-16214-0_9
A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models.
Sotiriou-Xanthopoulos, E.; Delicia, G. S. P.; Figuli, P.; Siozios, K.; Economakos, G.; Becker, J.
2015. 2015 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2015, Greece, 70-77, IEEE. doi:10.1109/SAMOS.2015.7363661
Parametric design space exploration for optimizing QAM based high-speed communication.
Delicia George Ford, S. P.; Figuli, P.; Becker, J.
2015. IEEE/CIC ICCC 2015 Symposium on Communication and Control Theory : IEEE/CIC International Conference on Communications in China, ICCC 2015; Shenzhen; China; 2 November 2015 through 5 November 2015, Art.Nr.: 7448662, IEEE, Piscataway (NJ). doi:10.1109/ICCChina.2015.7448662
2013
Proceedingsbeiträge
Bringing Accuracy to Open Virtual Platforms (OVP): A Safari from High-Level Tools to Low-Level Microarchitectures.
Shalina, G.; Bruckschloegl, T.; Figuli, p.; Tradowsky, C.; Almeida, G.; Becker, J.
2013. Proceedings on International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences, ICIIIOSP-2013, Dec. 2013, 22-27, Foundation of Computer Science, New York (NY)