Development of a hardware accelerator for Graph Neural Networks for object recognition in embedded systems
Artificial intelligence has found its way into many areas and is now the de facto standard in image processing. Models that use a large database to learn to solve predefined tasks are often used. Among the emerging models are Graph Neural Networks (GNNs). But for the benefits of artificial intelligence to reach mobile end-user applications, it needs to be embedded and adapted to the limited hardware constraints.
In this thesis, the performance-accuracy tradeoff of hardware acceleration of GNN-based object recognition on FPGA is to be evaluated. For this purpose, a hardware-aware model is to be developed first, which is then brought onto an FPGA using high-level synthesis. Optionally, compression possibilities shall be investigated to optimize the overall system with respect to energy efficiency and real-time capability. The hardware accelerator is to be integrated into an existing robotic system.
- Programming experience in Python and C++
- Basic knowledge of neural networks
- Experience in hardware design is an advantage
- Motivation and interest in solving technical problems independently