Project InvasIC

Collaborative Research Center/Transregio 89 - Invasive Computing - InvasIC

Under the term Invasive Computing, a completely new paradigm for the design and programming of future parallel computing systems is explored. The basic idea is to give parallel programs the ability to distribute computations to a set of currently available resources in a phase known as invasion in a resource-aware manner, and after parallel processing to release them in a phase known as retreat. To efficiently enable this new type of self-adaptive and resource-aware programming on future MPSoCs (Multi-Processor-Systems-on-a-Chip), new programming concepts, languages and compilers as well as runtime or operating systems are required, as well as revolutionary architectural inventions related to the reconfigurability of both processor, interconnect and memory resources.


B1 Adaptive, application-specific, invasive microarchitectures.

B1 investigates mechanisms that provide adaptivity in instruction set (ISA) and microarchitecture (μArch) using run-time reconfigurable hardware. We will explore concepts and methods to invade this hardware and μArch within an i-core. The goals are to extend the concepts of leading reconfigurable processors for invasive computing and to harness their advantages. The focus is on i) investigating runtime adaptivity of the μArch, ii) on-demand provisioning of i-let-specific ISA, and iii) dynamic acceleration of basic invasion commands and runtime system.

B5 Invasive NoCs - autonomous, self-optimizing communication infrastructures for embedded multiprocessor systems.

B5 addresses the research and design of invadable on-chip communication networks (so-called iNoCs) with a focus on three key problems: a) definition of necessary protocols and router functionalities for communication channel invasion, b) characterization and run-time prediction of communication traffic to improve data throughput and resource utilization, and c) decentralized strategies for cost-effective embedding of application-specific communication patterns and topologies taking into account latency barriers, competing invasion requests as well as temporary link failures.

Z2 Validation and Demonstrator

Subproject Z2 describes the FPGA-based demonstration platform needed to a) evaluate early concepts of invasive hardware, software, and algorithms, b) reduce risks for subsequent invasive ASIC design, and c) prototype a heterogeneous invasive MPSoC since simulation approaches are not applicable in terms of complexity and accuracy.

Links to the project website:



  • FAU: Friedrich-Alexander University Erlangen-Nuremberg
  • TUM: Technical University of Munich


Photos from project meetings:

Annual meeting in Blaubeuren, 15-16 September 2016 (report on the meeting at


Semi-annual meeting 14.02.2011


Team subarea Z2


Project meeting in Pommersfelden