Tobias Dörr, M.Sc.

Tobias Dörr, M.Sc.

  • Engesserstr. 5

    76131 Karlsruhe

Research interests

Model-based design of safety-critical embedded systems

Modern embedded systems used in domains such as automotive or aerospace are subject to increasingly stringent safety and real-time requirements. To cope with the complexity that is associated with the development of such systems, novel design paradigms based on formal models are becoming increasingly important. In this context, we develop modeling techniques and, based on these techniques, software tools that automatically transform given model instances into reliable implementation artifacts.

Synthesis of isolation mechanisms for modern mixed-criticality systems

To meet their performance requirements, modern embedded systems are increasingly based on multicore processors. This is often accompanied by a tight integration of subsystems with different criticality levels. To ensure that a sufficient degree of safety and security is achieved despite this integration, reliable isolation mechanisms must be incorporated into the systems. We investigate approaches that perform an automatic generation of such mechanisms by leveraging available hardware capabilities.

Fault tolerance mechanisms based on dynamic hardware redundancy

As automated driving functions are on the rise, the risk of electronic malfunctions in the vehicle leading to physical harm is increasing. Therefore, components that are relevant in this context must often be designed in such a way that they reliably deliver a defined minimum level of functionality despite such malfunctions. This requires the use of suitable fault tolerance mechanisms. We are researching how the concept of dynamic hardware redundancy can be used to implement such mechanisms a particularly cost-effective manner.

Available student works

Bachelor and master theses in the context of the current research activities are avilable. Depending on your interest, these works can be focused on the modeling of HW/SW systems, the implementation of isolation and fault tolerance mechanisms, or a combination of both fields. The proposals shown below are suggestions that can be adapted to the desired focus.

Supervised student works

  • MA: “Development of a Configurable Access Protection Module for FPGA Components”
  • SA: “Evaluation of Cost-Efficient Fault Detection Approaches for MPSoC-Based Fail-Operational Systems”
  • MA: “Development of an FPGA-Controlled Architecture for Dynamic On-Chip Redundancy of Safety-Critical Functions”
  • MA: “Optimization of a Code Generator for Isolation Configurations of Modern MPSoCs”

Publications


2021
Journal Articles
Model-based configuration of access protection units for multicore processors in embedded systems.
Dörr, T.; Sandmann, T.; Becker, J.
2021. Microprocessors and microsystems, 87, Article no: 104377. doi:10.1016/j.micpro.2021.104377
Achieving cost-efficient fail-operational behavior based on inherent redundancy at the system level.
Dörr, T.; Sandmann, T.; Friederich, P.; Leitner, A.; Becker, J.
2021. Microprocessors and microsystems, 87, Aricle no: 104380. doi:10.1016/j.micpro.2021.104380
Conference Papers
Employing the Concept of Multilevel Security to Generate Access Protection Configurations for Automotive On-Board Networks.
Dörr, T.; Sandmann, T.; Mohr, H.; Becker, J.
2021. 2021 24th Euromicro Conference on Digital System Design (DSD), 107–114, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD53832.2021.00026
2020
Conference Papers
An Approach to Cost-Efficient Fault Tolerance in Inherently Redundant Fail-Operational Systems.
Dörr, T.; Sandmann, T.; Friederich, P.; Leitner, A.; Becker, J.
2020. 2020 23rd Euromicro Conference on Digital System Design (DSD), 630–637, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD51259.2020.00103
A Formal Model for the Automatic Configuration of Access Protection Units in MPSoC-Based Embedded Systems.
Dörr, T.; Sandmann, T.; Becker, J.
2020. 2020 23rd Euromicro Conference on Digital System Design (DSD), 596–603, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD51259.2020.00098
2019
Conference Papers
Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems.
Dörr, T.; Sandmann, T.; Schade, F.; Bapp, F. K.; Becker, J.
2019. Applied Reconfigurable Computing – 15th International Symposium, ARC 2019, Darmstadt, 9.-11. April 2019, 96–111, Springer. doi:10.1007/978-3-030-17227-5_8
2018
Reports/Preprints