- Study of Electrical Engineering and Information Technology at KIT (2012 – 2017)
- Research assistant at ITIV since October 2017
- Exercises on “Hardware-Synthese und -Optimierung” (since 2019, in German)
- Model-based approaches to HW/SW integration in safety-critical embedded systems
- Isolation of hardware components in modern system-on-chip platforms
- Fault tolerance mechanisms based on dynamic hardware redundancy
Master thesis: “Development of a Configurable Access Protection Module for FPGA Components” (2020)
- Master thesis: “Development of an FPGA-Controlled Architecture for Dynamic On-Chip Redundancy of Safety-Critical Functions” (2020)
Bachelor and master theses as well as student assistant positions in the context of the current research activities are avilable. Depending on your interest, these works can be focused on the modeling of HW/SW systems (AADL, Java, ...), the implementation of isolation and fault tolerance mechanisms (VHDL, Verilog, C, ...), or a combination of both fields. The vacancies shown below are suggestions that can be adapted to the desired focus.
Dörr, T.; Sandmann, T.; Friederich, P.; Leitner, A.; Becker, J.
2020. 2020 23rd Euromicro Conference on Digital System Design (DSD), 630–637, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD51259.2020.00103
Dörr, T.; Sandmann, T.; Becker, J.
2020. 2020 23rd Euromicro Conference on Digital System Design (DSD), 596–603, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD51259.2020.00098
Dörr, T.; Sandmann, T.; Schade, F.; Bapp, F. K.; Becker, J.
2019. Applied Reconfigurable Computing – 15th International Symposium, ARC 2019, Darmstadt, 9.-11. April 2019, 96–111, Springer. doi:10.1007/978-3-030-17227-5_8
Bapp, F. K.; Dörr, T.; Sandmann, T.; Schade, F.; Becker, J.
2018. SAE International. doi:10.4271/2018-01-1072