Zusammenfassung der Dissertation

Titel: "RFET Reconfigurable Devices: Power Aware FPGA Architectures and Toolflow"

Ziel der Dissertation war es, im Rahmen des Projektes PARFAIT aktive Powermanagement Techniken in FPGA Architekturen einzuführen und zu untersuchen. Der vorgestellte Lösungsansatz nutzt feingranulare, partiell dynamische Rekonfiguration, um Applikationslogik zur Laufzeit temporär durch Managementlogik zu ersetzen.

Diese realisiert eine Messung der aktuellen Laufzeitverzögerung in den entsprechenden Logikelementen, wobei die Applikation nicht beeinflusst wird. Basierend auf den Messergebnissen wird die Laufzeitverzögerung dynamisch angepasst, um die statische Verlustleistung zu reduzieren.

Das System wurde mit RFET und SOI Technologie simuliert, wobei eine bis zu 36-fache Reduktion der statischen Verlustleistung erzielt wurde.

Publikationen

RVVe: A Minimal RISC-V Vector Processor for Embedded AI Acceleration
Schmidt, P.; Pfau, J.; Hotfilter, T.; Stammler, M.; Harbaum, T.; Becker, J.
2024. 2024 IEEE 37th International System-on-Chip Conference (SOCC), Dresden, 16th-19th September 2024, 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC62300.2024.10737723

RFET Reconfigurable Devices: Power Aware FPGA Architectures and Toolflow. Dissertation
Pfau, J.
2024, November 15. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000174452

Co-Simulating Region-Based Dynamic Voltage Scaling for FPGA Architecture Design
Pfau, J.; Hernandez, J.; Reuter, M.; Hofmann, K.; Becker, J.
2023. 2023 IEEE Nordic Circuits and Systems Conference (NorCAS), Aalborg, 31st October - 01st November 2023, 7 S., Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/NorCAS58970.2023.10305486

Automated Replacement of State-Holding Flip-Flops to Enable Non-Volatile Checkpointing
Kreß, F.; Pfau, J.; Kempf, F.; Schmidt, P.; He, Z.; Harbaum, T.; Becker, J.
2023. 2023 IEEE Nordic Circuits and Systems Conference (NorCAS), 31st October - 1st November 2023, Aalborg, Denmark, 1–7, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/NorCAS58970.2023.10305469

Broadband MIMO Testbed for the Development and Research on 6G
Nuss, B.; Groeschel, P.; Pfau, J.; Becker, J.; Vossiek, M.; Zwick, T.
2023. European Wireless 2022 ; 27th European Wireless Conference, Dresden, 19th - 21st September 2022, 89 – 91, VDE VERLAG GMBH

Design and Implementation of Staggered-SAR Azimuth-Processing
Marten, J. C.; Younis, M.; Krieger, G.; Pfau, J.; Unger, K.; Becker, J.
2023. 24th International Radar Symposium (IRS), Berlin, Germany, 24-26 May 2023, Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/IRS57608.2023.10172405

Reconfiguring an RFET Based Differential Amplifier
Reuter, M.; Kramer, A.; Krauss, T.; Pfau, J.; Becker, J.; Hofmann, K.
2022. 2022 IEEE 40th Central America and Panama Convention (CONCAPAN), 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/CONCAPAN48024.2022.9997726

A Unified SoC Lab Course: Combined Teaching of Mixed Signal Aspects, System Integration, Software Development and Documentation
Pfau, J.; Leys, R.; Neu, M.; Serdyuk, A.; Peric, I.; Becker, J.
2023. 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 5 S., Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISCAS46773.2023.10181679

LETSCOPE: Lifecycle Extensions Through Software-Defined Predictive Control of Power Electronics
Chu, A.; Hermann, C. M.; Silz, J.; Pfau, J.; Barón, K. M.; Anantharajaiah, N.; Schmidt, P.; Hotfilter, T.; Xie, X.; Becker, J.; Kallfass, I.; Roth-Stielow, J.; Stork, W.
2023. IEEE EUROCON 2023 - 20th International Conference on Smart Technologies, 665–670, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/EUROCON56442.2023.10199076

ReLoDAQ: Resource-Efficient, Low-Overhead 200 Gbits −1 Data Acquisition System for 6G Prototyping
Karle, C.; Neu, M.; Pfau, J.; Sperling, J.; Becker, J.
2023. 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 08-11 May 2023, Marina Del Rey, CA, USA, 209, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/FCCM57271.2023.00037

Designing Universal Logic Module FPGA Architectures for Use With Ambipolar Transistor Technology
Pfau, J.; Reuter, M.; Hofmann, K.; Becker, J.
2021. 2020 International Conference on Field-Programmable Technology (ICFPT), Maui, HI, USA, 09-11 December 2020, 165–173, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ICFPT51103.2020.00031

V-FPGAs: Increasing Performance with Manual Placement, Timing Extraction and Extended Timing Modeling
Pfau, J.; Zaki, P. W.; Becker, J.
2022. Journal of Signal Processing Systems, 94, 865–882. doi:10.1007/s11265-022-01786-z

A hardware/software co-design approach to prototype 6G mobile applications inside the GNU Radio SDR Ecosystem using FPGA hardware accelerators
Karle, C. M.; Kreutzer, M.; Pfau, J.; Becker, J.
2022. HEART2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba Japan, June 9 - 10, 2022, 33–41, Association for Computing Machinery (ACM). doi:10.1145/3535044.3535049

Evaluation of Different Manual Placement Strategies to Ensure Uniformity of the V-FPGA
Pfau, J.; Zaki, P. W.; Becker, J.
2021. Applied Reconfigurable Computing. Architectures, Tools, and Applications: 17th International Symposium, ARC 2021, Virtual Event, June 29–30, 2021, Proceedings. Ed.: S. Derrien, 35–49, Springer-Verlag. doi:10.1007/978-3-030-79025-7_3

From MOSFETs to Ambipolar Transistors: Standard Cell Synthesis for the Planar RFET Technology
Reuter, M.; Pfau, J.; Krauss, T. A.; Becker, J.; Hofmann, K.
2021. IEEE transactions on circuits and systems / 1, 68 (1), 114–125. doi:10.1109/TCSI.2020.3035889

A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s
Pfau, J.; Reuter, M.; Harbaum, T.; Hofmann, K.; Becker, J.
2020. 2019 32nd IEEE International System-on-Chip Conference (SOCC), Singapore, 3-6 Sept. 2019, 294–299, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC46988.2019.1570548289

Towards Ambipolar Planar Devices: The DeFET Device in Area Constrained XOR Applications
Reuter, M.; Pfau, J.; Krauss, T. A.; Moradinasab, M.; Schwalke, U.; Becker, J.; Hofmann, K.
2020. Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems (LASCAS), San Jose, Costa Rica, February 15-28, 2020, Article No. 9069043, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/LASCAS45839.2020.9069043

From MOSFETs to Ambipolar Transistors: A Static DeFET Inverter Cell for SOI
Reuter, M.; Krauss, T. A.; Moradinasab, M.; Pfau, J.; Schwalke, U.; Becker, J.; Hofmann, K.
2019. Proceedings. 2019 IEEE Asia Pacific Conference on Circuits and Systems : Royal Orchind Sheraton Hotel and Towers Bangkok, Thailand, November 11-14, 2019, 113–116, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/APCCAS47518.2019.8953083

Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems
Pfau, J.; Figuli, S. P. D.; Bähr, S.; Becker, J.
2018. Applied Reconfigurable Computing - Architectures, Tools, and Applications, Proceedings of the 14th International Symposium, ARC 2018, Santorini, Greece, 2nd - 4th May 2018. Ed.: Nikolaos Voros, 615–626, Springer. doi:10.1007/978-3-319-78890-6_49

Development of a Latency Optimized Communication Device for WAVE and SAE Based V2X-Applications
Pistorius, F.; Lauber, A.; Pfau, J.; Klimm, A.; Becker, J.
2016. SAE technical papers, 2016-April, 1–11. doi:10.4271/2016-01-0150