Empowering Tomorrow's Engineers: An MLIR-Based Toolchain for Transforming Python Neural Networks into Verilog Hardware

Context

Neural networks are an ideal target for implementation on an FPGA. Their simple architecture, consisting solely of dataflow elements, has enabled the design of architectures with high throughput and low latency. However, modern networks introduce control flow elements that limit the effectiveness of static scheduling used by today’s HLS tools. To overcome this, dynamic high-level synthesis allows the designer to make localized scheduling decisions using classical handshake signals.

Tasks

Attention, aspiring engineers! Join us in a significant endeavor. This thesis explores the conversion of Python neural networks into Verilog hardware. Using MLIR and LLVM, we’re delving into the depths of high-level synthesis, bringing algorithms to dynamic hardware.

This project isn’t just another task; it’s the genuine, hands-on work that is reshaping the landscape of hardware design. We’re earnestly exploring the intricate blend of machine learning and synthesis. It’s a chance to contribute to the future of technology and make a tangible impact.

Join us on this journey of knowledge and innovation. Together, let’s pioneer a new chapter in hardware design. 

Requirements

• Knowledge of C++
• Knowledge of hardware design is a plus
• Interest in embedded design