Hella Toto Kiesa, M.Sc.
- Member of Scientific Staff
- Group: Prof. Becker
- Phone: +49 721 608-41309
- hella kiesa ∂does-not-exist.kit edu
Engesserstr. 5
76131 Karlsruhe
Neuromorphic Computing - Hardware-Algorithm-Co-Design
Neuromorphic computing mimics the functioning of the human brain, which is known for processing complex information efficiently and quickly. In systems such as edge computing or software-defined vehicles, efficiency and speed are of high relevance. They also play a significant role in medicine and healthcare, for example, in pattern recognition or sensor processing. Innovative memory concepts like Near-Memory Computing (NMC) enable energy-efficient data processing by bringing the computing logic closer to the memory, while on-chip communication methods optimize data transfer w ithin the chip. By co-optimizing hardware and algorithms (e. Spiking Neural Networks), this efficiency can be maximized.
AI Hardware Accelerators
AI applications and models are continuously evolving and increasingly require more resources. Embedded systems are characterized, among other things, by their compactness and the associated resource constraints. Therefore, computing power, memory, and energy must be used efficiently to fully exploit the advantages of these systems. Dedicated FPGA-based AI hardware accelerators are particularly suitable for this due to their high adaptability and flexibility. The goal is to research suitable optimization methods and concepts to maximize efficiency and performance in processing AI workloads.
Hardware-Software Co-Optimization for Embedded AI
Modern neural networks often exceed the capacity of a single embedded device. By partitioning a network across multiple, sometimes heterogeneous computing units, latency, energy consumption, and memory requirements can be significantly reduced. However, the automated partitioning and distribution of AI workloads across heterogeneous hardware is complex and requires new methods to sensibly divide and coordinate the computational load among the participating systems.
Selection of Student Projects (Completed)
- “Partitioning and Mapping of Spiking Neural Networks” (BA)
- “Mapping-Aware Spiking Neural Architecture Search” (BA)
Publications
Gutermann, A.; Serdyuk, A.; Lesniak, F.; Hoefer, J.; Toto Kiesa, H.; Harbaum, T.; Becker, J.; Pachideh, B.; Nitzsche, S.; Neher, M.; Weigelt, C.; Krausse, J.; Pazmino, V.; Knobloch, K.; Groth, L.; Nešković, A.; Mulhem, S.; Berekovic, M.
2026. 2026 Design, Automation & Test in Europe Conference (DATE), 1–7, Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/DATE69613.2026.11539165
Friedrich, M.; Lüders, M.; Renke, O.; Weddige, S.; Riggers, C.; Blume, H.; Friedrich, S.; Mojumder, S.; Matúš, E.; Fettweis, G.; Ahmadifarsani, S.; Kontopoulos, L.; Schlichtmann, U.; Hoefer, J.; Schmidt, P.; Toto-Kiesa, H.; Becker, J.; Kock, M.; Schewior, G.; Blume, S.; Grantz, D.; Benndorf, J.; Fasfous, N.; Mori, P.; Voegel, H.-J.; Teepe, G.; Bierzynski, K.
2025. Mikroelektronik, Mikrosystemtechnik und ihre Anwendungen - Nachhaltigkeit und Technologiesouveranitat, MikroSystemTechnik Congress 2025 - Microelectronics, Microsystems Technology and their Applications - Sustainability and Technological Sovereignty, MicroSystemTechnology Congress 2025, 399–403, VDE VERLAG GMBH
Gutermann, A.; Serdyuk, A.; Paraskevas, F.; Toto Kiesa, H.; Lesniak, F.; Schwarz, J.; Hartmann, M.; Harbaum, T.; Becker, J.
2025. 2025 IEEE Nordic Circuits and Systems Conference, NorCAS 2025, Riga, 28th-29th October 2025, 1–7, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/NorCAS66540.2025.11231285
Hoefer, J.; Schmidt, P.; Toto-Kiesa, H.; Hoefer, S.; Schewior, G.; Engelke, D.; Eickel, K.-H.; Grantz, D.; Harbaum, T.; Becker, J.
2025. Proceedings of the Great Lakes Symposium on VLSI 2025, 704–711, Association for Computing Machinery (ACM). doi:10.1145/3716368.3735208