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Praktikum Entwurfsautomatisierung

Praktikum Entwurfsautomatisierung

ITIV, Vincenz-Prießnitz-Str. 1, Karlsruhe, building 07.07, room 227/242

start: 04.05.2009

Prof. Dr.-Ing. Klaus D. Müller-Glaser
Dipl.-Ing. Lukasz Niestoruk
Dipl.-Ing. Christian Schuck

sws: 4
ects: 6
lv-no.: 23637
exam: 27.07.2009

The exam will take place on Juli 27th 2009, 2 p.m., at Gaede lecture hall.

Praktikum Entwurf digitaler Systeme (PES)/ Digital Hardware Design Laboratory (DHL)


Fundamentals of Electronic Systems Design (e.g. SAE, course code 23606, HSO, course code 23619 and HMS, course code 23608).




The Digital Hardware Design Laboratory (DHL) is part of the TivSeg laboratory projects at ITIV. This laboratory focuses on the FPGA logic of the TivSeg system, which is responsible for processing camera input data. The FPGA-based image processing subsystem represents the basic prerequisite for autonomously driving segways.

In this laboratory, students practically apply development and simulation techniques known from the lectures. In DHL, students use the development and synthesis tools from Xilinx as well as the simulation tool ModelSim from Mentor Graphics, which are both widely-used in the industry. The sources developed in the laboratory are tested on an industrial grade hardware platform.
The target platform of the laboratory is the Digilent ZEDBOARD, which is equipped with a Xilinx Zynq System-on-Chip (SoC). The Zynq combines FPGA logic modules with a dual core ARM processor on a single chip.

In the first part of the laboratory, students learn the fundamentals of the synthesis and simulation tools as well as the hardware description language Very High Speed Integrated Circuit Hardware Description Language (VHDL). An introduction to the laboratory including the handling of the different tools and learning VHDL is given during the first four laboratory afternoons.
First of all, students are introduced to the basic components of an FPGA and learn how to create bitstreams, which can be used to program the FPGA. Subsequently, basic knowledge on the creation of testbenches is imparted, which enable students to verify their self-written modules. An additional laboratory afternoon focuses on describing finite state machines in VHDL, which are essential for the flow control in hardware designs. Furthermore, students learn to instantiate highly optimized hard-blocks, which can simplify the design of complex circuits tremendously. During the last introduction afternoon, students learn how to develop their own VHDL-modules based on given boundary conditions.
This is done by means of the implementation of an efficient signed –divider module. Additionally, the connection of self-written components to the bus system of the Zynq ARM processor is imparted.

In the subsequent actual implementation part of the laboratory, students develop a hardware accelerator for camera image processing using the Zynq FPGA module. The RGB data provided by the camera is read out by the ARM processor, which transmits it to the FPGA logic using the bus system. The logic then extracts prominent areas (regions) from the image and transmits the results back to the processor. The processor can now control the TivSeg system based on this information or visualize the detected regions on a monitor connected to the HDMI interface of the ZEDBOARD.