Design and implementation of a Deep Neural Network hardware accelerator for face recognition on FPGA.

Environment

Artificial intelligence has entered many fields to make systems for e.g. image recognition, speech processing or motion analysis more precise and reliable than previous hand-optimized algorithms allow. One common method is supervised Deep Learning (DL). In this process, deep neural networks learn to solve predefined tasks themselves with the help of a large database. But for artificial intelligence to enrich mobile end-user applications, it must be embedded and adapted to limited hardware conditions.

Task

In this thesis, the hardware acceleration of DL-based face recognition on FPGA is to be evaluated. The hardware accelerator is to be embedded into an existing robotic system. For this purpose, compression options such as quantization and pruning are to be investigated in order to optimize the overall system with respect to energy efficiency and real-time capability.

Requirements

• Programming experience in Python and C++
• Basic knowledge of neural networks
• Motivation and interest in solving technical problems independently