Design of a hardware module for graph-based neural networks in the context of the Belle II experiment.
- Type:Masterarbeit
- Date:offen (zu vergeben)
- Tutor:
Design of a hardware module for graph-based neural networks in the context of the Belle II experiment.
Environment
ITIV is working as a project partner of the Belle II experiment in Tsukuba, Japan on the next generation of trigger systems for particle accelerators. As part of a detector upgrade, the luminosity of the experiment will be increased step by step. In this context, we are exploring how the FPGA-based trigger system can be better adapted for the increasing data volumes.
Task
With the next upgrade of the Belle II particle accelerator, Graph Neural Networks (GNNs) will be used in a trigger system for the first time. The necessary graphs have to be generated online in the system. Within the scope of this work, a hardware module for building the graphs will be developed and implemented on an FPGA. In addition, it will be investigated to what extent the developed module is suitable for the implementation of GNNs.
Prerequisites
- Interest in Machine Learning and FPGAs
- Experience with HLS, C++ or VHDL is advantageous.