Real-time noise reduction using graph signal processing methods in the Belle II project.
ITIV is working as a project partner of the Belle II experiment in Tsukuba, Japan on the next generation of trigger systems for particle accelerators. As part of a detector upgrade, the luminosity of the experiment will be increased step by step. In this context, we are exploring how the FPGA-based trigger system can be adapted for increasing data rates.
The planned upgrades to the Belle II particle accelerator will significantly degrade the signal-to-noise ratio in the central drift chamber. In order to distinguish interesting particle collisions from background noise, an improvement of the signal processing capabilities in the level 1 trigger is required. Within the scope of this study, graph signal processing methods are investigated for filter applications in high-throughput, low-latency environments. Demonstrating the feasibility of the developed concept, the implementation of suitable algorithms shall be evaluated on real-time FPGA platforms.
- Interest in graph signal processing, machine learning or FPGAs
- First knowledge in programming (Python, C++, VHDL, Verilog)