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Design and Evaluation of Unum based DSP Blocks for FPGA Architectures

Design and Evaluation of Unum based DSP Blocks for FPGA Architectures
type:Masterarbeit
time:available
tutor:

M. Sc. Johannes Pfau

Design and Evaluation of Unum based DSP Blocks for FPGA Architectures

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Context

In previous research projects, ITIV has developed the V-FPGA, an in-house, custom FPGA architecture. This FPGA architecture currently mostly consists of the basic building blocks: Lookup Tables, flip-flops and components for  signal routing. Modern commercial FPGAs  in addition include arithmetic processing blocks: So-called DSP which are primarily used for digital signal processing. These blocks usually support integer or fixed-point operation and support for floating point is not common. In regards to floating point representations, the unum / posit number format has recently been suggested as an alternative to the IEEE representation in computer science.

 

Task

The main task of this work is to evaluate the suitability of unum for arithmetic blocks in FPGAs. For this evaluation, first a literature research and assessment of DSPs in existing FPGA architectures should be carried out. Then an unum accelerator should be implemented or adapted as a DSP block for integration into the V-FPGA architecture. After the core has been integrated into the architecture and into the tools, it shall be evaluated using some benchmark signal processing applications. In addition, a reference integer DSP shall be developed or adapted for comparison, evaluating area and performance differences between the unum and fixed point implementation.

 

Prerequisites

VHDL or Verilog knowledge recommended