Background

The upcoming Belle II particle collider experiment is the most modern particle detector experiment in the world. It will target a world record Luminosity, which corresponds to the number of particle collisions over time. The resulting amount of data to be saved for later analysis of the experiment is simply too huge to get across the data transmission lines. Fortunately, a huge chunk of data is produced by effects that are not important for the experiment, as they don’t result in new knowledge. Identifying this data early on allows discarding uninteresting data, while saving only relevant data. This approach solves the data transmission problem.
More Information:  https://www.belle2.org/
At the ITIV we are researching, implementing and integrating so called trigger mechanisms on FPGAs for Belle II. These are deciding over the readout of the detector during the collisions. A significant part of that system is the Track Segment Finder, which use geometric figures use to narrow the angle to 30°. The current Track Segment Finder is implemented in VHDL as State Machine. Due to the many changes there is no reference implementation.

Task of the Thesis

The main task of this thesis is a new implementation of the Track Segment Finder reference in C and the implementation of a Hardwar/Software Co-Design Simulation.

1. Familiarization phase
   1. Orientation in design of the actual Track Segment Finder
   2. Familiarization with Hardwar/Software Co-Design
2. Concept- and design phase
   1. Develop a C Implementation of the Track Segment Finder
   2. Decide how the reference and the VHDL files are tested
3. Implementation phase
   1. Implementation of the Concept
   2. Evaluation of Track Segment Finders in a Hardwar/Software Co-Design Simulation
4. Documentation
   1. Creation of a documentation covering the topics described above

Language

German / English