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An Implementation of Dynamic Intra-Tile Reallocatable L1 Cache in homogeneous GPPs

An Implementation of Dynamic Intra-Tile Reallocatable L1 Cache in homogeneous GPPs
type:Masterarbeit
time:available
tutor:

M. Sc. Arthur Silitonga
M. Sc. Fabian Lesniak

An Implementation of Dynamic Intra-Tile Reallocatable L1 Cache in homogeneous GPPs

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Fig. 1(a)
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Fig. 1(b)

Background

The Network-on-Chip (NoC) architecture of an Invasive Computing (InvasiC) Platform is depicted in      Fig. 1(a). The architecture itself contains many tiles interconnected via routers in a meshed grid. A tile may consist of four identical General Purpose Processors (GPPs) based on the SPARC V8 architecture. Specifically, the LEON3 Processor, developed according to the SPARC V8 architecture, is used in the platform and will share a L1 cache within a tile.

The shared L1 cache, called dynamic intra-tile reallocatable cache (DIRCA), is the main topic of this thesis as it has to be implemented on FPGA. In the implementation, the DIRCA shall be reconfigurable during run time to parameterize the cache blocks for each core. The size and associativity of  allocated blocks in the DIRCA may change dynamically. The general illustration of the DIRCA in one tile of the NoC is shown in Fig. 1(b).

 

 

Main tasks

  • Develop and implement a DIRCA for homogeneous GPPs in a tile
  • Analyze and monitor the DIRCA’s performance
  • Implement a use case (optional)
 

Required skills/ knowledge

  • Student of electrical engineering or computer science
  • Basic knowledge in computer architecture
  • Experience in FPGA-based hardware dev.
  • Eagerness to learn the concept of dynamic reconfiguration and its impl. on FPGA