Overview

Embedded electronic systems are subject to a variety of different requirements. Above all, the demand for computing power has steadily increased for decades. To cover this, the use of modern processors in multi-core and networked architectures is unavoidable. Increases in complexity however make such architectures more susceptible to random failures, causing potentially catastrophic effects. Radiation can randomly affect transistor cells (Fig. 1), causing the running application to behave unpredictably and unreliably.

Fig. 1 Hochenergie-Neutronen-Effekte an einem N-MOS-Transistor

Safety-critical environments in domains such as avionics, aerospace and automated driving pose a massive challenge to the evolution of computational power: despite the complexity of using such advanced technologies, the system must still meet existing reliability and availability requirements. As we develop new techniques and architectures to achieve such goals, we must be able to test and collect information to properly validate new functionalities.

The development of a minimal operating system kernel with Synchronous Multi Processing (SMP) capabilities for the evaluation of fault tolerant and fault operational techniques is the subject of this research.

Tasks description

The main objective of this work is the implementation of multi-processing extensions for the existing free real-time operating system FreeRTOS for embedded devices. The target platform that will run this extended kernel is Xilinx’s Zynq Family of embedded SoCs. The implementations should first focus on the dual-Core Zynq-7010 series and eventually also be ported to the quad-Core Zynq-UltraScale+ series of devices.

The resulting system software should keep current FreeRTOS functionalities for single core, creating a new system library, where all new functionalities should be implemented. Any modifications to existing Kernel functions should be minimum. All system management functions should only execute on one master core (e.g. Core 0). This master core through interruptions, wake-up events and other synchronization mechanisms will then control the remaining cores (see Fig. 2).

Fig. 2 Beispiel SMP Setup mit 1 Master Core und 3 SMP Cores zur Bearbeitung der Tasks

Requirements

The theoretical part of this thesis requires knowledge of embedded electronic systems as well as familiarity with program memory management and Inter Process Communications. For the practical part, good programming skills are required. A detailed list of skills follows:

• Knowledge of embedded C and/or Assembler programming is required.
• Knowledge of embedded CPU architectures and Operating Systems is desired.
• Experience with Zynq and Vivado tools is helpful.