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Florian Schade, M. Sc.

Florian Schade, M. Sc.

Member of Scientific Staff
group: Prof. Becker
room: 125.2
CS 30.10

phone: +49 721 608-41972
fax: +49 721 608-42511
florian schadeTev9∂kit edu

Engesserstr. 5

76131 Karlsruhe

M. Sc. Florian Schade

Curriculum Vitae

  • B. Sc. in Electrical Engineering and Information Technology at KIT
    • Graduated in December 2013
    • Bachelor Thesis: Simulated Network Localization by Signal Strength and Time-of-Flight Measurements in Ultra-Wideband-Networks
  • M. Sc. in Electrical Engineering and Information Technology at KIT
    • Specialization: Systems Engineering
    • Graduated in November 2016
    • Master Thesis: Design, Integration, and Evaluation of a Misbehavior Detection Concept for Vehicular Ad-Hoc Networks
  • Employee at ITIV since March 2017
Studentische Arbeiten
Titel Datum


Methodical approach for the development of a platform for the configuration and operation of turnkey production systems.
Gönnheimer, P.; Kimmig, A.; Mandel, C.; Stürmlinger, T.; Yang, S.; Schade, F.; Ehrmann, C.; Klee, B.; Behrendt, M.; Schlechtendahl, J.; Fischer, M.; Trautmann, K.; Fleischer, J.; Lanza, G.; Ovtcharova, J.; Becker, J.; Albers, A.
2019. Procedia CIRP, 84, 880–885. doi:10.1016/j.procir.2019.04.260
Evaluation of a high-throughput communication link for future automotive ADAS controllers.
Yigui, L.; Youteng, S.; Schade, F.; Hotfilter, T.; Becker, J.; Yuan, Z.; Zizhou, O.; Weiming, L.
2019. Proceedings of the Institution of Mechanical Engineers / D, 233 (9), 2371–2378. doi:10.1177/0954407019851334
Modular smart controller for Industry 4.0 functions in machine tools.
Barton, D.; Gönnheimer, P.; Schade, F.; Ehrmann, C.; Becker, J.; Fleischer, J.
2019. Procedia CIRP, 81, 1331–1336. doi:10.1016/j.procir.2019.04.022
Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems.
Dörr, T.; Sandmann, T.; Schade, F.; Bapp, F. K.; Becker, J.
2019. Applied Reconfigurable Computing – 15th International Symposium, ARC 2019, Darmstadt, 9.-11. April 2019, 96–111, Springer, Cham, CH. doi:10.1007/978-3-030-17227-5_8
HLS-based Performance and Resource Optimization of Cryptographic Modules.
Silitonga, A.; Schade, F.; Jiang, G.; Becker, J.
2018. Proceedings of the 16th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA2018), Melbourne, Australia, 11th-13th December 2018, 1009–1016, IEEE. doi:10.1109/BDCloud.2018.00147
Towards Fail-Operational Systems on Controller Level Using Heterogeneous Multicore SoC Architectures and Hardware Support.
Bapp, F. K.; Dörr, T.; Sandmann, T.; Schade, F.; Becker, J.
2018. SAE International, Warrendale (PA). doi:10.4271/2018-01-1072