Arthur Silitonga, M. Sc.

Arthur Silitonga, M. Sc.

  • Engesserstraße 5
    76131 Karlsruhe

Research interests

High-Level Synthesis and Software-defined Multiprocessor SoC

High-level Synthesis (HLS) and Software-defined MPSoC (SDSoC) are at the higher abstraction (software) levels in design and development methodologies of tools. Both methodologies will be explored, applied in use cases, especially security-related ones for Unmanned Aerial System, and optimized to implement designs in FPGA and other components in SoC. Phases in HLS tools are the research's primary attention, and its possible interconnection to SDSoC is the secondary one. With the HLS, the complexity of FPGA-based design and development should be reduced using a higher abstraction approach.
 

Hardware Security and Applied Cryptography

The security aspect in a specific application domain will be investigated, and the aspect relates to the implementation of some designs in FPGA and other components in a heterogeneous SoC. Applied Cryptography is the central instance of this topic in providing confidentiality and integrity to accesses and designs developed, optimized, and implemented in FPGA or SoC. In addition, improving security-related aspects in implementing cryptography will be analyzed and considered. Trojan detection and anti-piracy mechanism for designs in FPGA are minor aspects of this topic.  
 

Reconfigurable Architectures in Multiprocessor SoC

The context of reconfigurable architectures relates the design and development in the higher abstraction layer in HLS or SDSoC. RTL-Coding-based design and development will be used in only certain cases. Indeed, optimizations of the designs are crucial instead of providing security-related features to designs in the FPGA and other components of Multiprocessor SoC. From this point of view, optimizations are also concerned with methods or techniques in the static configuration or dynamic reconfiguration of designs from a higher abstraction level to logic synthesis/binary level of SoC/FPGA.

Supervised student works (selection)

  • MA: “Untersuchung von High-Level Synthese zur Entwicklung eines Kryptographiemoduls für rekonfigurierbare Hardwareplattformen“
  • MA: “Implementation and Evaluation of Partially Reconfigurable Multiple Symmetric Crypto Algorithms in SoC“
  • BA: “Implementation and Analysis of an Asymmetric Crypto Algorithm with Multiple Key Lengths Using Partial Reconfiguration in SoC“
  • MA: “Introduction and the Influence of Microarchitectural Attacks at Processing System of a System-on-Chip“
  • BA: “The Cutting-Edge Concepts and Basic Implementation of Attack in CAN-Bus Network“
  • MA: “Channel Estimation of Dynamic Intra-Tile Reallocatable Cache in Homogeneous GPPs“

Publications


2021
Journal Articles
Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis
Bannwart Perina, A.; Silitonga, A.; Becker, J.; Bonato, V.
2021. IEEE transactions on computers, 70 (12), 2070–2082. doi:10.1109/TC.2021.3112260
Conference Papers
HLS-centric DSE and Optimization for Dynamically Reconfigurable Elliptic Curve Cryptography (ReCC)
Silitonga, A.; Kiyak, Y.; Becker, J.
2021. 2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID), 122–128, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ASID52932.2021.9651483
Security-driven Cross-Layer Model & Description of a HW/SW Framework for AP MPSoC-based Computing Device
Silitonga, A.; Becker, J.
2021. The 14th IEEE International Systems Conference (SYSCON), Montreal, Canada (Virtual), 24-27 August, 2020, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SysCon47679.2020.9353653
2020
Conference Papers
MiteS: Software-based Microarchitectural Attacks and Countermeasures in networked AP SoC Platforms
Silitonga, A.; Gassoumi, H.; Becker, J.
2020. The 14th IEEE International Conference on Anti-counterfeiting, Security, and Identification (ASID), Xiamen, China (Virtual), Oct. 31-Nov. 1, 2020, 65–71, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ASID50160.2020.9271734
2019
Conference Papers
Reconfigurable Module of Multi-mode AES Cryptographic Algorithms for AP SoCs
Silitonga, A.; Jiang, Z.; Khan, N.; Becker, J.
2019. 2019 IEEE Nordic Circuits and Systems Conference (NorCAS), Helsinki, FIN, October 29-30, 2019, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/NORCHIP.2019.8906923
Secure Local Configuration of Intellectual Property Without a Trusted Third Party
Khan, N.; Silitonga, A.; Pachideh, B.; Nitzsche, S.; Becker, J.
2019. Applied reconfigurable computing : 15th international symposium, ARC 2019, Darmstadt, Germany, April 9-11, 2019 : proceedings, 137–146, Springer. doi:10.1007/978-3-030-17227-5_11
2018
Conference Papers
HLS-based Performance and Resource Optimization of Cryptographic Modules
Silitonga, A.; Schade, F.; Jiang, G.; Becker, J.
2018. Proceedings of the 16th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA2018), Melbourne, Australia, 11th-13th December 2018, 1009–1016, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/BDCloud.2018.00147
2015
Conference Papers
An emulation of transparent interface design based on TCP/IP implemented onto FPGA of an Altera Nios® Board
Silitonga, A.; Hutabarat, M.
2015. 2015 9th International Conference on Telecommunication Systems Services and Applications (TSSA), Bandung, 25–26 November 2015, Art.Nr. 7440432, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/TSSA.2015.7440432
2014
Conference Papers
Concept implementation of sole module for software-based UL subframe mapping method on a TDD WiMAX IEEE 802.16e-based Subscriber Station
Silitonga, A.; Adiono, T.; Wicaksono, I.
2014. 2014 2nd International Conference on Information and Communication Technology (ICoICT), Bandung, Indonesia, 28–30 May 2014, 340–345, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ICoICT.2014.6914089
Evaluation of X2-handover performance based on RSRP measurement with Friis path loss using network simulator version 3 (NS-3)
Assyadzily, M.; Suhartomo, A.; Silitonga, A.
2014. 2014 2nd International Conference on Information and Communication Technology (ICoICT), Bandung, Indonesia, 28–30 May 2014, 436–441, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ICoICT.2014.6914102
Ontology-based knowledge representation of failure mode and effect analysis on Electric/Electronic Architecture modeling conforming to the ISO 26262
Silitonga, A.; Hillenbrand, M.
2014. 2014 International Conference of Advanced Informatics: Concept, Theory and Application (ICAICTA), Bandung, Indonesia, 20–21 August 2014, 260–265, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ICAICTA.2014.7005951
A new approach of quantum-inspired genetic algorithm for self-generation of fuzzy logic controller
Bukhori, I.; Silitonga, A.
2014. 2014 IEEE International Conference on Intelligent Autonomous Agents, Networks and Systems (INAGENTSYS), BANDUNG, Indonesia, 19–21 August 2014, 30–35, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/INAGENTSYS.2014.7005721
2013
Conference Papers
Infrared Depth Sensor Kinect-based Smart Room Controller
Silitonga, A.; Thoeng, S.
2013. Proceedings of 2014 IEEE Sensors Applications Symposium (SAS); Queenstown, New Zealand; February, 18-20, 2014
Blind and lighting control to maintain comfort light intensity of the classroom utilizing Microcontroller ATmega8535
Silitonga, A.; Indrawan, I. G. L. W.
2013. 2013 International Conference on Information Technology and Electrical Engineering (ICITEE), Yogyakarta, Indonesia, 7–8 October 2013, 438–443, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ICITEED.2013.6676282