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Dipl.-Inform. Steffen Bähr

Scientific Staff
Group Leader Neuromorphic and High Speed Processing
group: Prof. Becker
room: 127
CS 30.10

phone: +49 721 608-42509
fax: +49 721 608-42511
steffen baehrHfh2∂kit edu

Engesserstr. 5

76131 Karlsruhe

Dipl.-Inform. Steffen Bähr


Studied Computer Science at KIT, finished with university diploma

  • Major Courses
    • Design of embedded systems and computer architecture
    • Software architecture and compiler construction
  • Ergänzungsfach
    • Systems Engineering
  • Diploma thesis
    • Design and Implementation of virtualization support for hardware accelerator / Konzept und Implementierung einer Virtualisierungsünterstützung für Hardwarebeschleuniger


Research assistant at ITIV since 2013   





  • Virtualization support for shared hardware accelerators : Modern automotive systems will require employment of multicore technology to keep up with the developments of the semiconducter industry. Using such systems in such safety critical systems requires extra care to ensure that interference by using shared hardware resources can be managed. One approach for this is to isolate applications of mixed criticality in separate virtual machines. However the necessary environment will induce an performance overhead, espescially for managing shared access to hardware. For this techniques to reduce this overhead both on a software and hardware level are researched. An example is an infrastructure for shared access to an FPGA based accelerator over PCIe.
  • Data Reduction and trigger for high luminosity particle detector experiments :  Modern High luminosity particle detectors like Belle-II generate massive data rates during runtime. Readout of all data is costly and not necessary, since a huge part of the data is not coming from particle collisions, but from other effects that will steer a particle towards the detector. Data reduction and trigger schemes are employed online on FPGAs to deal with this problem. They will either reduce the total amount of data readout or the readout frequency. However they have identify particles coming from the collision precisely and in low latency, few ns, to avoid losing valubale information and buffer overflow at the detector readout. A new approach for these schemes is to use algorithms based on neural networs. The online cluster analysis and neural z-Vertex trigger are two such examples developed here in this research group
  • Hardware accelerators with brainlike architecture: Data processing based on emulation of brainlike structures is a hot topic in the hardware accelerator community. They can be an effective solution for modern classification tasks. Meanwhile key figures of merit like throughput, latency and power can be optimized by using dedicated accelerators. Examples can be realtime high throughput maintenance prediction on FPGAs based on sensor data of machines, such a system was developed in our group.




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Dipl.-Inform. Steffen Bähr
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