Dr.-Ing. Dipl.-Inform. Leonard Masing

Dr.-Ing. Dipl.-Inform. Leonard Masing

  • Engesserstr. 5

    76131 Karlsruhe

Research interests

Toolchains for the safety-critical domain

Providing guarantees that an implementation meets its specified requirements is essential in the safety-critical domain. The tasks of verifying and validating given requirements and constraints is especially challenging considering the increasing demands for software functionality that meet high-performance concurrent multicore platforms. Consequently, advanced toolchains are needed that support the developer by highlighting critical issues while increasing the level of automation in the design process.

Dependable high-performance multicore platforms

Multi-core systems with an increasing number of cores and specialized accelerators for tasks such as AI have become a commodity for increasing the performance of today’s compute platforms. However, combining high-performance features with dependability and predictability is still a major challenge. At the same time, platforms need to be both flexible and specialized to achieve maximum performance under strict power constraints.

Co-design and co-emulation of hardware and software

Efficient computing systems need to employ a well-balanced conjunction of hardware and software. Avoiding bottlenecks while delivering the required performance under all given constraints makes a consequent co-design process necessary that employs techniques for early prototyping and co-emulation of the system under design.

Student works to be assigned

Titel

Supervised student works (selection)

  • BA: "High-Level-Synthese für das Design Networks on Chip; High-level Synthesis for the Design of Networks on Chip"

  • MA: "Entwicklung einer effizienten und skalierbaren Umgebung für das NoC-Prototyping; Development of an Efficient and Scalable NoC Prototyping Environment"

  • MA: "Konzept, Evaluation und Implementierung einer echtzeitfähigen Speicherinfrastruktur für Many-Core Systeme; Concept, Evaluation and Implementation of a Real-Time Capable Memory Infrastructure for Many-Core Systems"

  • BA: "Dynamisches Circuit switching im invasiven NoC; Dynamic circuit switching in the invasive NoC"

  • Projektarbeit: "Cross-Domain Prototyping of NoC-Based Many-Core Platforms"

  • BA: "Anbindung eines Instruction Set Simulators an das iNoC Simulations-framework; Connection of an Instruction Set Simulator to the iNoC Simulation Framework"

  • BA: "Aufbau und Evaluation einer Circuit switching Erweiterung des invasiven NoC in SystemC; Implementation and Evaluation of a Circuit Switching Extension of the Invasive NoC in SystemC"

  • BA: "Intelligente kamerabasierte Fahrer-Assistenz-Systeme für ein Roadtrain Szenario"

  • BA: "Parallelisierung der High-level Simulation (OVP) einer Multicore-Plattform; Parallelization of the High-level simulation (OVP) of a multicore platform"

Publications


2021
Journal Articles
A Hybrid Prototyping Framework in a Virtual Platform Centered Design and Verification Flow
Masing, L.; Lesniak, F.; Becker, J.
2021. IEEE embedded systems letters, 13 (1). doi:10.1109/LES.2020.2995084
Conference Papers
Xandar: X-by-Construction Design framework for Engineering Autonomous & Distributed Real-time Embedded Software Systems
Becker, J.; Masing, L.; Dörr, T.; Schade, F.; Keramidas, G.; Antonopoulos, C. P.; Mavropoulos, M.; Tiganourias, E.; Kelefouras, V.; Antonopoulos, K.; Voros, N.; Durak, U.; Ahlbrecht, A.; Zaeske, W.; Panagiotou, C.; Karadimas, D.; Adler, N.; Sailer, A.; Weber, R.; Wilhelm, T.; et al.
2021. Proceedings 2021 31st International Conference on Field-Programmable Logic and Applications: FPL 2021 ; Dresden, Germany, 30 August – 3 September 2021, 382–383, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/FPL53798.2021.00075
2020
PhD Theses
Prototyping Methodologies and Design of Communication-centric Heterogeneous Many-core Architectures. PhD dissertation
Masing, L. J.
2020, November 26. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000126812
2019
Conference Papers
A Network on Chip Adapter for Real-Time and Safety-Critical Applications
Kempf, F.; Anantharajaiah, N.; Masing, L.; Becker, J.
2019. 32nd IEEE International System on Chip Conference, SOCC 2019; Singapore; Singapore; 3 September 2019 through 6 September 2019. Ed.: D. Zhao, 39–44, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC46988.2019.1570558594
Dynamic and scalable runtime block-based multicast routing for networks on chips
Anantharajaiah, N.; Kempf, F.; Masing, L.; Lesniak, F. M.; Becker, J.
2019. Proceedings of the 12th International Workshop on Network on Chip Architectures (NoCArc 2019), Columbus, OH, Ocober 12-13, 2019, 1–6, Association for Computing Machinery (ACM). doi:10.1145/3356045.3360718
Hybrid Prototyping for Manycore Design and Validation
Masing, L.; Lesniak, F.; Becker, J.
2019. 15th International Symposium on Applied Reconfigurable Computing, ARC 2019; Darmstadt; Germany; 9 April 2019 through 11 April 2019, 319–333. doi:10.1007/978-3-030-17227-5_23
2018
Journal Articles
OpenCL-based Virtual Prototyping and Simulation of Many-Accelerator Architectures
Sotiriou-Xanthopoulos, E.; Masing, L.; Xydis, S.; Siozios, K.; Becker, J. Ü.; Soudris, D.
2018. ACM transactions on embedded computing systems, 17 (5), Article: 86. doi:10.1145/3242179
Conference Papers
In-NoC Circuits for Low-Latency Cache Coherence in Distributed Shared-Memory Architectures
Masing, L.; Srivatsa, A.; Kreß, F.; Anantharajaiah, N.; Herkersdorf, A.; Becker, J.
2018. IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Hanoi, VN, September 12-14, 2018, 138–145, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MCSoC2018.2018.00033
A WCET-Aware Parallel Programming Model for Predictability Enhanced Multi-core Architectures
Reder, S.; Masing, L.; Bucher, H.; Braak, T. ter; Stripf, T.; Becker, J.
2018. Proceedings of the 2018 Design, Automation & Test in Europe (DATE) : 19-23 March 2018, Dresden, Germany. Ed. J. Madsen, 943–948, Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/DATE.2018.8342145
Presentations
In-NoC circuits for low-latency cache coherence in distributed shared-memory architectures
Masing, L.; Srivatsa, A.; Kreß, F.; Anantharajaiah, N.; Herkersdorf, A.; Becker, J.
2018. 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2018), Hanoi, Vietnam, September 12–14, 2018
2016
Conference Papers
A Novel NoC-Architecture for Fault Tolerance and Power Saving
Heisswolf, J.; Friederich, S.; Masing, L.; Weichslgartner, A.; Zaib, A.; Stein, C.; Duden, M.; Teich, J.; Herkersdorf, A.; Becker, J.
2016. Proceedings of the second International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS). 5. April 2016, Nürnberg, Institute of Electrical and Electronics Engineers (IEEE)
A Novel ADL-based Approach to Design Adaptive Application-Specific Processors
Tradowsky, C.; Harbaum, T.; Masing, L.; Becker, J.
2016. Best of ISVLSI 2016, Pittsburgh, Pennsylvania, U.S.A., July 11-13, 2016, Springer
An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures
Sotiriou-Xanthopoulos, E.; Masing, L.; Siozios, K.; Economakos, G.; Soudris, D.; Becker, J.
2016. International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XVI), Samos, GR, July 17-21, 2016. Proceedings. Ed.: W. Najjar, 372–377, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SAMOS.2016.7818375
2015
Conference Papers
Software-in-the-Loop simulation of embedded control applications based on Virtual Platforms
Werner, S.; Masing, L.; Lesniak, F.; Becker, J.
2015. 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, United Kingdom, 2–4 September 2015, Art.Nr. 7294020, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/FPL.2015.7294020
Virtual prototyping of heterogeneous dynamic platforms using Open Virtual Platforms
Masing, L.; Werner, S.; Becker, J.
2015. 2015 10th IEEE International Symposium on Industrial Embedded Systems (SIES), Siegen, Germany, 8–10 June 2015, 152–155, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SIES.2015.7185053
Fault-tolerant Communication in Invasive Networks on Chip
Heisswolf, J.; Weichslgartner, A.; Zaib, A.; Friederich, S.; Masing, L.; Duden, M.; Klöpfer, R.; Teich, J.; Wild, T.; Herkersdorf, A.; Becker, J.
2015. Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, June 15-18, 2015, Montreal, Canada, Art.Nr. 7231156. doi:10.1109/AHS.2015.7231156
Designing applications for heterogeneous many-core architectures with the FlexTiles Platform
Janßen, B.; Schwiegelshohn, F.; Koedam, M.; Duhem, F.; Masing, L.; Werner, S.; Huriaux, C.; Courtay, A.; Wheatley, E.; Goossens, K.; Lemonnier, F.; Millet, P. T.; Becker, J.; Sentieys, O.; Hübner, M.
2015. 15th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2015, Samos, Greece, 254–261, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SAMOS.2015.7363683