Latency-optimised optical link for multi-FPGA neural network implementation

Latency-optimised optical link for multi-FPGA neural network implementation

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Background:

FPGAs with their flexibility and speed have proven a great platform for implementing modern neural networks. Nevertheless, the ever-growing demands of NN applications push resource utilization of FPGA devices to its limit. One of the effective potential ways to overcome this limitation is to ensure scalability of neural networks across multiple FPGA devices. Major advantages of this approach are the degree of scalability and cost-efficiency.
The bottleneck of the multi-FPGA neural network inference is in the latency of communication links. Commonly, such links use buffers that make communication latency relatively high and variable, which is unacceptable in numerous safety-critical real-time application, e.g. automotive systems. This work is aimed at overcoming this bottleneck by designing a latency-optimised optical communication link.

You will learn:

Low-level fundamentals of time-critical optical communication with Xilinx GTH transceivers.

Tasks and responsibilities:

  • Review prior work on multi-FPGA neural network implementations
  • Integrate a demonstrator system with one link between FPGA boards (Xilinx ZCU102)
  • Prepare and execute a performance evaluation procedure for the demonstrator

Requirements:

  • Knowledge of VHDL and Linux (user level)
  • Experience in handling Vivado projects (incl. constraints and top-level module)
  • Interest in communication protocols