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Stripf

Dr.-Ing. Timo Stripf

Wissenschaftlicher Mitarbeiter
Raum: 218.2
Tel.: +49 721 608-46884
Fax: +49 721 608-42511
timo stripfXeh4∂kit edu

Engesserstr. 5

76131 Karlsruhe



Dr.-Ing. Timo Stripf

Lebenslauf

  • Geboren April 1982
  • Studium der Informatik an den Universität Karlsruhe (TH)
  • Seit Oktober 2007 Wissenschaftlicher Mitarbeiter am ITIV

Forschung

  • Design-Space Exploration basierend auf einem retargierbaren Compilerframework
  • Compiler Design für rekonfigurierbare Befehlssatzprozessoren
  • Processor Design (Rekonfigurierbare Prozessor, Superskalarität, VLIW, Event-Driven Prozessoren)
  • Kahrisma

Lehre

  • Hardware/Software Codesign

 

Studentische Arbeiten

Dr. Timo Stripf
Titel Datum
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Publikationen


2017
Zeitschriftenaufsätze
Grafisch parallel programmieren.
Oey, O.; Stripf, T.
2017. Elektronik, (9), 48-51
Proceedingsbeiträge
Interaktive Parallelisierung von Anwendungen für eingebettete Mehrkernprozessoren.
Stripf, T.; Oey, O.
2017. parallel 2017, Softwarekonferenz für Parallel Programming, Concurrency, HPC und Multicore-Systeme, Heidelberg, 29.-31. März 2017
Increasing Energy Efficiency Through Semi-Automatic Parallelization of Applications for Embedded Computing Devices in the IoT Domain.
Oey, O.; Rueckauer, M.; Stripf, T.; Becker, J.
2017. Embedded World Conference 2017, 14. bis 16. März 2017, Nürnberg
WCET-aware parallelization of model-based applications for multi-cores : The ARGO approach.
Derrien, S.; Puaut, I.; Alefragis, P.; Bednara, M.; Bucher, H.; David, C.; Debray, Y.; Durak, U.; Fassi, I.; Ferdinand, C.; Hardy, D.; Kritikakou, A.; Rauwerda, G.; Reder, S.; Sicks, M.; Stripf, T.; Sunesen, K.; Ter Braak, T.; Voros, N.; Becker, J.
2017. Proceedings of the 20th Design, Automation and Test in Europe, Lausanne, Switzerland, 27-31 March 2017, 286-289, IEEE, Piscataway (NJ). doi:10.23919/DATE.2017.7927000
2013
Hochschulschriften
Zeitschriftenaufsätze
Compiling Scilab to high performance embedded multicore systems.
Stripf, T.; Oey, O.; Bruckschloegl, T.; Becker, J.; Rauwerda, G.; Sunesen, K.; Goulas, G.; Alefragis, P.; Voros, N. S.; Derrien, S.; Sentieys, O.; Kavvadias, N.; Dimitroulakos, G.; Masselos, K.; Kritharidis, D.; Mitas, N.; Perschke, T.
2013. Microprocessors and Microsystems, 37 (8 Part C), 1033-1049. doi:10.1016/j.micpro.2013.07.004
Proceedingsbeiträge
Coarse-grain optimization and code generation for embedded multicore systems.
Goulas, G.; Valouxis, C.; Alefragis, P.; Voros, N. S.; Gogos, C.; Oey, O.; Stripf, T.; Bruckschloegl, T.; Becker, J.; El Moussawi, A.; Naullet, M.; Yuki, T.
2013. Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, 4-6 September 2013, Santander, Spain. Ed.: J. S. Matos, 379-386, IEEE, Piscataway (NJ). doi:10.1109/DSD.2013.48
A flexible implementation of the PSO algorithm for fine-and coarse-grained reconfigurable embedded systems.
Rueckauer, M.; Munoz, D. M.; Stripf, T.; Oey, O.; Llanos, C. H.; Becker, J.
2013. 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013, Cancun, Mexico December 9-11, 2013. Ed.: R. Cumplido, IEEE, Piscataway (NJ). doi:10.1109/ReConFig.2013.6732293
2012
Proceedingsbeiträge
A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture.
Stripf, T.; Koenig, R.; Becker, J.
2012. Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'12), Dresden, March 12-16, 2012. Ed.: K. Preas, 21-26, IEEE, Piscataway (NJ)
A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files.
Stripf, T.; Koenig, R.; Becker, J.
2012. 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW'12), Shanghai, China, May 21-25, 2012; Vol. 1, 462 - 469, IEEE, Piscataway (NJ)
A flexible approach for compiling scilab to reconfigurable multi-core embedded systems.
Stripf, T.; Oey, O.; Bruckschloegl, T.; Koenig, R.; Huebner, M.; Becker, J.; Goulas, G.; Alefragis, P.; Voros, N. S.; Rauwerda, G.; Sunesen, K.; Derrien, S.; Menard, D.; Sentieys, O.; Kavvadias, N.; Dimitroulakos, G.; Masselos, K.; Goehringer, D.; Perschke, T.; Kritharidis, D.; u. a.
2012. Proceedings of the 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'12), York, United Kingdom, July 9-11, 2012. Ed.: L. S. Indrusiak, 8 S., IEEE, Piscataway (NJ). doi:10.1109/ReCoSoC.2012.6322879
2011
Proceedingsbeiträge
Architecture Design Space Exploration of Run-Time Scalable Issue-Width Processors.
Koenig, R.; Stripf, T.; Heisswolf, J.; Becker, J.
2011. Proceedings of the International Conference on Embedded Computer Systems (SAMOS'11), Samos, Greece, July 18-21, 2011. Ed.: L. Carro, 77 - 84, IEEE, Piscataway (NJ)
A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors.
Koenig, R.; Stripf, T.; Heisswolf, J.; Becker, J.
2011. Proceedings of the IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW'11), Anchorage, Alaska, USA, May 16-20, 2011, 150-157, IEEE, Piscataway (NJ)
A novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors.
Stripf, T.; Koenig, R.; Becker, J.
2011. International Conference on Embedded Computer Systems (SAMOS 2011), Samos, Greece, July 18 - 21, 2011. Ed.: L. Carro, 157-164, IEEE, Piscataway (NJ)
2010
Proceedingsbeiträge
KAHRISMA: A Novel Hypermorphic Reconfigurable- Instruction-Set Multi-grained-Array Architecture.
Becker, J.; Koenig, R.; Stripf, T.; Bauer, L.; Henkel, J.; Shafique, M.; Ahmed, W.
2010. Proceedings of the 2010 Design, Automation & Test in Europe Conference & Exhibition, DATE 2010, Dresden, Germany, 8 - 12 March 2010, Vol. 1, 819 - 824, IEEE, Piscataway (NJ)
2008
Buchaufsätze
A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms.
Koenig, R.; Stripf, T.; Becker, J.
2008. DATE 2008 - Design, Automation and Test in Europe, 10 - 14 March 2008, Munich, Germany, 604 - 609, IEEE Service Center, Piscataway (NJ)