Short Bio/CV:
- Bachelor of Science, Electrical Engineering, Institut Teknologi Bandung (ITB), Indonesia
- Bachelor Final Year’s Project: An Interface Design based on TCP/IP Protocol and its Implementation onto FPGA - Altera® Nios Board
- Master of Science, Faculty of Electrical Engineering and Information Technology, Karlsruher Institut für Technologie (KIT)
- Concentration: Information and Communications Engineering
- Master Thesis: Development and Evaluation of a Generic Prototyping Environment for ASIC & FPGA
- Doktorand/Research Assistant at ITIV since December 2016
Research/Forschung:
- Sichere und Lizenzierbare heterogene Ein-Chip Systeme (SiLiSys)
