- P. Figuli, C. Tradowsky, J. A. Lucio Martinez, H. Sidiropoulos, K. Siozos, H. Stenschke, D. Soudris, J. Becker
A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware
In Applied Reconfigurable Computing, Band 9040, S. 311-320, 2015
Zusammenfassung:
Today, digital signal processing systems for applications like audio or video production are restricted as they do not exhaust the possibilities given by modern hardware. Reconfigurable hardware exploits a huge degree of parallelism and provides flexibility at an affordable energy budget, thus becoming a competitive alternative for high performance Digital Signal Processing (DSP) applications, previously dominated by general purpose processing cores and Application-Specific Integrated Circuits (ASICs). This paper describes the design and evaluation of a novel concept for adaptive signal processing on reconfigurable hardware by using an adaptive reverberation algorithm targeting real time streams. Novel solutions were adopted in several critical parts of the signal processing chain in order to achieve a high level of accuracy under real time constraints. Experimental results show the efficiency of the introduced implementation on a Virtex-7 FPGA, as we can provide reality accurate reverberation with ultra low latency of ∼20.8μs.
BibTeX: Anzeigen
- K. Siozos, P. Figuli, H. Sidiropoulos, C. Tradowsky, K. Maragos, G. Shalina, D. Soudris, J. Becker
TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools
(Nominated as Best Paper Candidate)
In Applied Reconfigurable Computing, Band 9040, S. 103-114, 2015
Zusammenfassung:
This paper presents an on-going collaboration project, named TEAChER for providing breakthrough knowledge to students and young researchers on reconfigurable computing and advanced digital systems. The project is intended to cover topics like architectures and capabilities of field-programmable gate arrays, languages for the specification, modeling, and synthesis of digital systems. Furthermore design methods, computer-aided design tools, reconfiguration techniques and practical applications are taught. The virtual laboratory enables the remote students to easily interact with a set of reconfigurable platforms in order to control experiments through the internet. By using the user-friendly interface, the remote user can change predefined system parameters and observe system response either in textual, or graphical format. In addition such a virtual laboratory includes a booking system, which enables remote users to conduct experiments in advance.
BibTeX: Anzeigen
- M. Birk, E. Kretzek, P. Figuli, M. Weber, J. Becker, N. Ruiter
High-Speed Medical Imaging in 3D Ultrasound Computer Tomography
In Parallel and Distributed Systems, IEEE Transactions on, 2015
Zusammenfassung:
A promising candidate for sensitive imaging of breast cancer is 3D Ultrasound Computer Tomography (3D USCT). So far its clinical applicability for diagnosis has been limited by the duration of the demanding image reconstruction. In this paper we investigate how signal processing and image reconstruction can be accelerated for diagnosis by using heterogeneous hardware. Additionally, the time and costs for real-time system for a future diagnosis and therapy device is estimated. Reusing the device’s built-in FPGA-based data acquisition system (DAQ) through reconfiguration results in a speed-up by a factor of 7 for signal processing and by a factor of 2 for image reconstruction. Applying cutting-edge single FPGAs and GPUs, speed-ups by a factor of 10 (FPGA) and 6 (GPU) for signal processing and 15 (FPGA) and 37 (GPU) for image reconstruction were achieved compared to a recent quad-core Intel Core-i7 CPU. Using quad-core CPUs and a cluster of eight GPUs allowed us for the first time to calculate volumes in less than 30 min with an overall speed-up by a factor of 47, enabling a first clinical study. Based on these results we extrapolated that real-time reconstruction for a therapeutic 3D USCT will be possible in the year 2020 if the trend in density follows the ITRS roadmap.
BibTeX: Anzeigen
- S. Figuli, A. Sonnino, P. Figuli, J. Becker
A Variable FPGA Based Generic QAM Transmitter with Scalable Mixed Time and Frequency Domain Signal Processing
In 39th International Conference on Telecommunications and Signal Processing, 2016
Zusammenfassung:
Momentan nicht verfügbar
Download:
Momentan nicht verfügbar
BibTeX: Anzeigen
Zusammenfassung:
Momentan nicht verfügbar
Download:
Momentan nicht verfügbar
BibTeX: Anzeigen
- E. Sotiriou-Xanthopoulos, G. Shalina, P. Figuli, K. Siozos, G. Economakos, J. Becker
A Power Estimation Technique for Cycle-Accurate Higher-Abstraction SystemC-based CPU Models
In International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2015
Zusammenfassung:
Due to the ever-increasing complexity of embedded
system design and the need for rapid system evaluations in
early design stages, the use of simulation models known as
Virtual Platforms (VPs) has been of utmost importance as they
enable system modeling at higher abstraction levels. Since a
typical VP features multiple interdependent components, VP
libraries have been utilized in order to provide off-the-shelf
models of commonly-used hardware components, such as CPUs.
However, CPU power estimation is not adequately supported by
existing VP libraries. In addition, existing power characterization
techniques require architectural details which are not always
available in early design stages. To address this issue, this paper
proposes a technique for power annotation of CPU models
targeting SystemC/TLM libraries in order to enable the accurate
power estimation at higher abstraction levels. By using a set
of benchmarks on a power-annotated SystemC/TLM model of
Xilinx Microblaze soft-processor, it is shown that the proposed
approach can achieve accurate power estimation in comparison
to the real-system power measurements as the estimation error
ranges from 0.47% up to 6.11% with an average of 2%.
Download:
Momentan nicht verfügbar
BibTeX: Anzeigen
Zusammenfassung:
Due to the ever-increasing complexity of embedded
system design and the need for rapid system evaluations in
early design stages, the use of simulation models known as
Virtual Platforms (VPs) has been of utmost importance as they
enable system modeling at higher abstraction levels. Since a
typical VP features multiple interdependent components, VP
libraries have been utilized in order to provide off-the-shelf
models of commonly-used hardware components, such as CPUs.
However, CPU power estimation is not adequately supported by
existing VP libraries. In addition, existing power characterization
techniques require architectural details which are not always
available in early design stages. To address this issue, this paper
proposes a technique for power annotation of CPU models
targeting SystemC/TLM libraries in order to enable the accurate
power estimation at higher abstraction levels. By using a set
of benchmarks on a power-annotated SystemC/TLM model of
Xilinx Microblaze soft-processor, it is shown that the proposed
approach can achieve accurate power estimation in comparison
to the real-system power measurements as the estimation error
ranges from 0.47% up to 6.11% with an average of 2%.
Download:
Momentan nicht verfügbar
BibTeX: Anzeigen
- G. Shalina, P. Figuli, J. Becker
Parametric Design Space Exploration for Optimizing QAM Based High-speed Communication
In IEEE/CIC International Conference on Communications in China, 2015
Zusammenfassung:
The growing demands on high-speed data transmission over long distances require optimized communication solutions with bandwidth efficient modulation techniques like Quadrature Amplitude Modulation (QAM). However, the various design parameters of QAM based communication systems are conflicting each other and the complex interdependence makes it difficult and time consuming to appropriately tune the parameters towards an optimal solution for a given set of constraints. Therefore, throughout this paper we analyze the various conflicting design parameters of QAM and derive objective optimized trade-offs. More specifically we study in detail the effects and interdependencies of parameters in the matched filter, the Forward Error Correction (FEC) code pair and the modulation order and span the design and solution space through experimental and numerical results. We discuss the observed effects and show how a selection of parameters can be concluded under various constraints. Furthermore, a pareto analysis on our design space points out the best combinations of modulation order, filter and FEC for maximizing the performance under various Signal-to-Noise Ratio (SNR) conditions of the channel. For instance, if the channel is constrained by an SNR of 10dB and the tolerable Bit Error Rate (BER) is 10^(-3), then 16-QAM with a required 2/3 FEC yields even a 33.3% higher performance than 64-QAM with a required 1/3 FEC. Thus, the outcomes of this paper are a comprehensive elaboration on the cross-effects of conflicting design parameters and a set of optimized solutions under various constraints.
Download:
Momentan nicht verfügbar
BibTeX: Anzeigen
Zusammenfassung:
The growing demands on high-speed data transmission over long distances require optimized communication solutions with bandwidth efficient modulation techniques like Quadrature Amplitude Modulation (QAM). However, the various design parameters of QAM based communication systems are conflicting each other and the complex interdependence makes it difficult and time consuming to appropriately tune the parameters towards an optimal solution for a given set of constraints. Therefore, throughout this paper we analyze the various conflicting design parameters of QAM and derive objective optimized trade-offs. More specifically we study in detail the effects and interdependencies of parameters in the matched filter, the Forward Error Correction (FEC) code pair and the modulation order and span the design and solution space through experimental and numerical results. We discuss the observed effects and show how a selection of parameters can be concluded under various constraints. Furthermore, a pareto analysis on our design space points out the best combinations of modulation order, filter and FEC for maximizing the performance under various Signal-to-Noise Ratio (SNR) conditions of the channel. For instance, if the channel is constrained by an SNR of 10dB and the tolerable Bit Error Rate (BER) is 10^(-3), then 16-QAM with a required 2/3 FEC yields even a 33.3% higher performance than 64-QAM with a required 1/3 FEC. Thus, the outcomes of this paper are a comprehensive elaboration on the cross-effects of conflicting design parameters and a set of optimized solutions under various constraints.
Download:
Momentan nicht verfügbar
BibTeX: Anzeigen
