Institut für Technik der Informationsverarbeitung

Radar Signal Synthesis for Target Simulation

Radar Signal Synthesis for Target Simulation

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Context

The current development of autonomous cars will require extremely reliable radar sensors in order to guarantee the safety of road users. Therefore, there will be a high interest in test environments which verify that automotive radars work as expected in all traffic scenarios. Radar target simulators (RTS) are capable of generating virtual radar targets which a radar sensors perceives as traffic objects.

In order to create these virtual targets, the transmitted radar signal must be analyzed and resynthesized with respect to the modifications a real radar target would apply to the signal (delay, signal strength & doppler shift). The signal then must be transmitted synchronously to the radar under test. The new RFSoC FPGA by Xilinx presents itself as the perfect implementation platform for this task.

 

Task

The goals of this thesis are:

  • Evaluation of radar signal analysis and resynthesis algorithms in Matlab
  • Implementation of synchronization and transmit methods on RFSoC FPGA
  • Integration test with a radar development board

 

Prerequisites

  • VHDL/Verilog knowledge recommended
  • Basic Matlab knowledge will be useful
  • FMCW-Radar knowledge helpful but not mandatory