Curriculum Vitae

• Born in April 1982
• Diploma of Computer Science (Dipl.-Inform.) at Universität Karlsruhe (TH)
• PhD student at ITIV since October 2007

Research

• Design-Space Exploration (DSE) based on a retargetable compiler framework
• Compiler design for reconfigurable Instruction Set Architecture (ISA) processors
• Processor Design (Reconfigurable processors, superscalar, VLIW, event-driven processors)
• Kahrisma

Teaching

• Hardware/Software Codesign

Latest publications

• J. Becker, T. Stripf, O. Oey, M. Huebner, S. Derrien, D. Menard, O. Sentieys, G. Rauwerda, K. Sunesen, N. Kavvadias, K. Masselos, G. Goulas, P. Alefragis, N. S. Voros, D. Kritharidis, N. Mitas, D. Goehringer
  From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach (Link)
  In Digital System Design (DSD), 2012 15th Euromicro Conference on, S. 114-121, 2012


• T. Stripf, O. Oey, T. Bruckschloegl, R. Koenig, J. Becker, G. Goulas, P. Alefragis, N. S. Voros, J. Potman, K. Sunesen, S. Derrien, O. Sentieys
  A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems (Link)
  In Computational Science and Engineering (CSE), 2012 IEEE 15th International Conference on, S. 383-390, 2012


• G. Goulas, P. Alefragis, N. S. Voros, C. Valouxis, C. Gogos, N. Kavvadias, G. Dimitroulakos, K. Masselos, D. Goehringer, S. Derrien, D. Menard, O. Sentieys, M. Huebner, T. Stripf, O. Oey, J. Becker, G. Rauwerda, K. Sunesen, D. Kritharidis, N. Mitas
  From Scilab to multicore embedded systems: Algorithms and methodologies (Link)
  In Embedded Computer Systems (SAMOS), 2012 International Conference on, S. 268-275, 2012


• T. Stripf, O. Oey, T. Bruckschloegl, R. Koenig, M. Huebner, G. Goulas, P. Alefragis, N. S. Voros, G. Rauwerda, K. Sunesen, S. Derrien, D. Menard, O. Sentieys, N. Kavvadias, G. Dimitroulakos, K. Masselos, D. Goehringer, T. Perschke, D. Kritharidis, N. Mitas, J. Becker
  A Flexible Approach for Compiling Scilab to Reconfigurable Multi-Core Embedded Systems (Link)
  In 2012 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip {(ReCoSoC)}, 2012


• T. Stripf, R. Koenig, J. Becker
  A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files
  In Parallel Distributed Processing, Workshops and Phd Forum (IPDPSW), 2012 IEEE International Symposium on, 2012

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