Curriculum Vitae

• Born in June 1978
• Studies "Elektrotechnik" at the University of Karlsruhe
• Since December 2005 Research Assistant at the ITIV

Research 

• heterogene Many-Core Systeme
• Transregio SFB "InvasIC" (DFG SFB/TRR89) - Invasives Rechnen
• "REFLECT" : Rendering FPGAs to Multi-Core Embedded Computing
• "ALMA" : ALgorithm parallelization for Multicore Architectures
• "Morpheus" : Multi-purpose dynamically Reconfigurable Platform for intensive Heterogeneous processing (abgeschlossen)

Latest publications

• C. Tradowsky, F. Thoma, M. Huebner, J. Becker
  LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture (Best Work-in-Progress (WiP) Paper Award) (Link)
  In Industrial Embedded Systems (SIES), 2012 7th IEEE International Symposium on, S. 279-282, 2012


• C. Tradowsky, F. Thoma, M. Huebner, J. Becker
  On Dynamic Run-Time Processor Pipeline Reconfiguration (Link)
  In Parallel and Distributed Processing Symposium Workshops PhD Forum (IPDPSW), 2012 IEEE 26th International, S. 419-424, 2012


• F. Thoma, M. Huebner, D. Goehringer, H. U. Yilmaz, J. Becker
  Power and performance optimization through MPI supported dynamic voltage and frequency scaling (Link)
  In Proc of the 3rd MARC Symposium, Ettlingen, Germany, 2011


• M. Huebner, C. Tradowsky, D. Goehringer, L. Braun, F. Thoma, J. Henkel, J. Becker
  Dynamic Processor Reconfiguration (Link)
  In Reconfigurable Computing and FPGAs (ReConFig), 2011 International Conference on, S. 123 -128, 2011


• A. Grasset, P. Brelet, P. Millet, P. Bonnot, F. Campi, N. Voros, M. Huebner, M. Kuehnle, F. Thoma, W. Putzke-Roeming, A. Schneider
  MORPHEUS: Exploitation of Reconfiguration for Increased Run-time Flexibility and Self-adaptive Capabilities in Future SoCs
  In Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, 2011

List publications according to year