deutsch  | Home | Legals | Data Protection | KIT

Simon Reder, M.Sc.

Member of Scientific Staff
group: Prof. Becker
room: Raum: 125.1
CS 30.10

phone: +49 721 608-42880
simon rederTeu6∂kit edu

Engesserstr. 5

76131 Karlsruhe

M. Sc. Simon Reder

Curriculum Vitae

  • Employee at the ITIV since 2014





  • Modelling and Simulation of digital Hardware/Software Systems

  • Parallel Simulation

  • Heterogeneous Computing









M. Sc. Simon Reder
title time


Mapping and Scheduling Hard Real Time Applications on Multicore Systems : The ARGO Approach.
Alefragis, P.; Theodoridis, G.; Katsimpris, M.; Valouxis, C.; Gogos, C.; Goulas, G.; Voros, N.; Reder, S.; Kasnakli, K.; Bednara, M.; Müller, D.; Durak, U.; Becker, J.
2018. Applied Reconfigurable Computing - Architectures, Tools, and Applications, Proceedings of the 14th International Symposium, ARC 2018, Santorini, Greece, 2nd - 4th May 2018. Ed.: C. Antonopoulos, 700–711, Springer, Cham. doi:10.1007/978-3-319-78890-6_56
A WCET-Aware Parallel Programming Model for Predictability Enhanced Multi-core Architectures.
Reder, S.; Masing, L.; Bucher, H.; ter Braak, T.; Stripf, T.; Becker, J.
2018. Proceedings of the 2018 Design, Automation & Test in Europe (DATE) : 19-23 March 2018, Dresden, Germany. Ed. J. Madsen, 943–948, IEEE, Piscataway (NJ). doi:10.23919/DATE.2018.8342145
WCET-aware parallelization of model-based applications for multi-cores : The ARGO approach.
Derrien, S.; Puaut, I.; Alefragis, P.; Bednara, M.; Bucher, H.; David, C.; Debray, Y.; Durak, U.; Fassi, I.; Ferdinand, C.; Hardy, D.; Kritikakou, A.; Rauwerda, G.; Reder, S.; Sicks, M.; Stripf, T.; Sunesen, K.; Ter Braak, T.; Voros, N.; Becker, J.
2017. Proceedings of the 20th Design, Automation and Test in Europe, Lausanne, Switzerland, 27-31 March 2017, 286–289, IEEE, Piscataway (NJ). doi:10.23919/DATE.2017.7927000
Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures.
Reder, S.; Roth, C.; Bucher, H.; Sander, O.; Becker, J.
2015. Microprocessors and microsystems, 39 (8), 1063–1075. doi:10.1016/j.micpro.2015.06.001
Adaptive Algorithm and Tool Flow for Accelerating SystemC on Many-Core Architectures.
Roth, C.; Reder, S.; Bucher, H.; Sander, O.; Becker, J.
2014. 17th Euromicro Conference on Digital System Design, DSD 2014; Verona; Italy; 27 August 2014 through 29 August 2014, 137–145, IEEE, Piscataway (NJ). doi:10.1109/DSD.2014.62
A SystemC modeling and simulation methodology for fast and accurate parallel MPSoC simulation.
Roth, C.; Bucher, H.; Reder, S.; Buciuman, F.; Sander, O.; Becker, J.
2013. 26th Symposium on Integrated Circuits and Systems Design (SBCCI’13), Curitiba, Brazil, September 2-6, 2013, 1–6, IEEE, Piscataway (NJ). doi:10.1109/SBCCI.2013.6644853
Improving parallel MPSoC simulation performance by exploiting dynamic routing delay prediction.
Roth, C.; Bucher, H.; Reder, S.; Sander, O.; Becker, J.
2013. 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC’13), Darmstadt, July 10-12, 2013, 1–8, IEEE, Piscataway (NJ). doi:10.1109/ReCoSoC.2013.6581524
A Framework for exploration of parallel SystemC simulation on the single-chip cloud computer.
Roth, C.; Reder, S.; Sander, O.; Huebner, M.; Becker, J.
2012. Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques, Desenzano del Garda, Italy, March 19-23, 2012. Ed.: G. Riley, 202–207, ICST, Brussels. doi:10.4108/icst.simutools.2012.247751
Asynchronous Parallel MPSoC Simulation on the Single-chip Cloud Computer.
Roth, C.; Reder, S.; Erdogan, G.; Sander, O.; Almeida, G.; Bucher, H.; Becker, J.
2012. 2012 International Symposium on System-on-Chip (SoC’12), Tampere, Finland, October 10-12, 2012, 8 S., IEEE, Piscataway (NJ)