Institut für Technik der Informationsverarbeitung

Dipl.-Inform. Steffen Bähr

  • Engesserstr. 5

    76131 Karlsruhe

Dipl.-Inform. Steffen Bähr

CV

Studied Computer Science at KIT, finished with university diploma

  • Major Courses
    • Design of embedded systems and computer architecture
    • Software architecture and compiler construction
  • Ergänzungsfach
    • Systems Engineering
  • Diploma thesis
    • Design and Implementation of virtualization support for hardware accelerator / Konzept und Implementierung einer Virtualisierungsünterstützung für Hardwarebeschleuniger

 

Research assistant at ITIV since 2013   

 

Education

 

Research

  • Virtualization support for shared hardware accelerators : Modern automotive systems will require employment of multicore technology to keep up with the developments of the semiconducter industry. Using such systems in such safety critical systems requires extra care to ensure that interference by using shared hardware resources can be managed. One approach for this is to isolate applications of mixed criticality in separate virtual machines. However the necessary environment will induce an performance overhead, espescially for managing shared access to hardware. For this techniques to reduce this overhead both on a software and hardware level are researched. An example is an infrastructure for shared access to an FPGA based accelerator over PCIe.
  • Data Reduction and trigger for high luminosity particle detector experiments :  Modern High luminosity particle detectors like Belle-II generate massive data rates during runtime. Readout of all data is costly and not necessary, since a huge part of the data is not coming from particle collisions, but from other effects that will steer a particle towards the detector. Data reduction and trigger schemes are employed online on FPGAs to deal with this problem. They will either reduce the total amount of data readout or the readout frequency. However they have identify particles coming from the collision precisely and in low latency, few ns, to avoid losing valubale information and buffer overflow at the detector readout. A new approach for these schemes is to use algorithms based on neural networs. The online cluster analysis and neural z-Vertex trigger are two such examples developed here in this research group
  • Hardware accelerators with brainlike architecture: Data processing based on emulation of brainlike structures is a hot topic in the hardware accelerator community. They can be an effective solution for modern classification tasks. Meanwhile key figures of merit like throughput, latency and power can be optimized by using dedicated accelerators. Examples can be realtime high throughput maintenance prediction on FPGAs based on sensor data of machines, such a system was developed in our group.

Sonstiges

 

Betreute abgeschlossene studentische Arbeiten

  • MA: "Area-Constrained 3D-Clustering for Real-Time Track Estimation Based on the Hough Transform"
  • BA: "Investigation and Implementation of Soft Error Mitigation and Detection for Belle II Trigger Modules"
  • BA: "Evaluierung und Entwicklung einer FPGA basierten Generierung  mehrdimensionaler Hough-Map; Evaluation and Development of a FPGA Based Multidimensional Hough Map Generation"
  • MA: "Entwurf einer hochspannungs CMOS integrierten Schaltung zur Spannungsregelung einer KFZ-Lichtmaschine mit programmierbarer Funktion"
  • MA: "HW/SW Co-Simulation for Validation and Evaluation of Trigger Components Using Physics Simulation Based on the Belle II Particle Detector Experiment"
  • MA: "Online Monitoring des neuronalen z-Vertex Triggers basierend auf dem Belle II Link; Online Monitoring of the Neural z-Vertex Trigger Based on Belle II Link"
  • MA: "Entwicklung einer 3D Spurfindung basierend auf der Hough Transformation auf FPGAs für den Driftkammer Trigger von Belle II; A 3D-Trackfinder Based on Hough Transformation on FPGAs for the Central Drift Chamber Trigger of Belle II"
  • MA: "Evaluierung und Untersuchung zukünftiger FPGA Plattformen für den Belle II z-Vertex Track Trigger in Phase 3"
  • BA: "Adaption des z-Vertex Triggers auf das VC709 Board und Erstellung eines Demonstrators der Belle II CDC DAQ; Adaptation of the z-Vertex Trigger to VC709 Board and Creation of a Demonstrator of the Belle II CDC DAQ"
  • BA: "Interfacing and Data Quality Management for the z-vertex Trigger of Belle II"
  • MA: "Entwurf und Implementierung neuronaler Netze auf FPGAs für den Z-Vertex Trigger von Belle II; Exploration and Development of Neural Networks on FPGAs for the Z-Vertex Trigger of Belle II"
  • DA: "Entwicklung und Evaluation einer flexiblen Architektur für Big-Data Anwendungen auf eingebetteten Plattformen"

 

Studentische Arbeiten

Dipl.-Inform. Steffen Bähr
Titel Datum

Publikationen


2020
Journal Articles
Conference Papers
2019
Journal Articles
Conference Papers
Reports/Preprints
2018
Conference Papers
2017
Journal Articles
2016
Journal Articles
2015
Journal Articles
Conference Papers
Reports/Preprints
2014
Conference Papers