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Hübner PD Dr.-Ing. Michael Hübner
room: 322
phone: +49 721 608-42504
fax: +49 721 608-42511
michael huebnerDpz3∂kit edu

Engesserstraße 5

76131 Karlsruhe

PD Dr.-Ing. Michael Hübner

Curriculum Vitae

  • Born in december of 1970
  • Scientific assistant at the ITIV since June 03



  • Adaptive run-time system with intelligent allocation for dynamically reconfigurable function patterns and optimized interface topologies
  • Dynamic and partial reconfiguration of Xilinx FPGAs
  • Cooperation project with DaimleChrysler/ITIV: "Rekonfigurierbare Hardware"
  • Network-On-Chip Architectures on FPGA




  • Program Chair der ReCoSoc 2008 (http://www-eel.upc.edu/recosoc/)
  • Program Chair des International Workshop on Reconfigurable Computing Education (RC-Education) 2008 (http://helios.informatik.uni-kl.de/RCeducation08/)
  • Publicity Chair der International Conference on Reconfigurable Computing and FPGAs (RECONFIG 2008) (www.reconfig.org)
  • Program Chair des International Workshop on Reconfigurable Computing Education (RC-Education) 2007 (http://helios.informatik.uni-kl.de/RCeducation07/)
  • Local Chair des IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006)
  • Program Commitee Member: The International Conference on Field-Programmable Logic, Reconfigurable Computing and Applications (FPL), IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Reconfigurable Architecture Workshop (RAW), Reconfigurable Co-Centric SoCs (ReCoSoc), HiPEACRC, Programm Chair des International Workshop on Reconfigurable Computing Education (RC-Education), IET Irish Signals and Systems Conference
  • Tutor of the HECTOR School Engineering and Management (the Technology Business School of KIT)
Dr.-Ing. Michael Hübner
title time

Latest publications

Journals & Books
  • T. Glock, M. Kern, S. Otten, E. Sax, M. Hillenbrand, M. Huebner
    Prozessanlagenplanung 2.0 - Netzarchitektur aus Verfahrensbeschreibung ableiten
    In DIV Vulkan Verlag, atp edition, Band vol. 58, no. 10, pp. 28-39, S. 28-39, 2016

  • A. Agmon, M. Nazarathy, D. Marom, S. Ben Ezra, A. Tolmachev, R. Killey, P. Bayvel, L. Meder, M. Huebner, W. Meredith, G. Vickers, P. C. Schindler, R. Schmogrow, D. Hillerkuss, W. Freude, C. Koos, J. Leuthold
    OFDM/WDM PON With Laserless, Colorless 1  Gb/s ONUs Based on Si-PIC and Slow IC
    In Journal of Optical Communications and Networking, Band 6, S. 225-237, 2014

  • H. Sidiropoulos, K. Siozos, P. Figuli, D. Soudris, M. Huebner, J. Becker
    JITPR: A Framework for Supporting Fast Application's Implementation onto FPGAs
    In ACM Transactions on Reconfigurable Technology and Systems (TRETS), Band 6, S. 7:1-7:12, 2013

Conferences & Workshops
  • B. Janßen, F. Schwiegelshohn, M. Koedam, F. Duhem, L. Masing, S. Werner, C. Huriaux, A. Courtay, E. Wheatley, K. Goossens, F. Lemonnier, P. Millet, J. Becker, O. Sentieys, M. Huebner
    Designing Applications for Heterogeneous Many-Core Architectures with the FlexTiles Platform
    In International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2015

  • G. Almeida, O. Longhi, T. Bruckschloegl, M. Huebner, F. Hessel, J. Becker
    Simplify: a Framework for Enabling Fast Functional/Behavioral Validation of Multiprocessor Architectures in the Cloud
    In 1st Workshop on Virtual Prototyping of Parallel and Embedded Systems, 2013

  • M. Ferger, A. Kadi, M. Koedam, M. Huebner, S. Sinha, K. Goossens, G. Almeida, J. R. Azambuja, J. Becker
    Hardware/Software Virtualization for the Reconfigurable Multicore Platform
    In , 2012

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