10 Publications of 2011
- M. Niknahad, O. Sander, L. Carro, J Azambuja, J. Becker, Fernanda Lima KastenSmidt
Using Quadded Logic in nanoPLAs to aggressively increase circuit yield
In NASNIT - 16th North-East Asia Symposium on Nano, Information Technology and Reliability, 2011 - M. Niknahad, O. Sander, J. Becker
FGTMR - Fine Grain Redundancy Method for Reconfigurable Architectures under high Failure Rates
In NASNIT, 16th North-East Asia Symposium on Nano, Information Technology and Reliability, 2011 - M. Niknahad, O. Sander, J. Becker
QFDR-an integration of Quadded Logic for modern FPGAs to tolerate high radiation effect rates
In Radecs - Conference on Radiation Effects on Components and Systems, 2011 - M. Niknahad, O. Sander, J. Becker
A study on fine granular fault tolerance methodologies for FPGAs
In RecoSoc, 2011 - J. Meyer, M. Huebner, L. Braun, O. Sander, J. Noguera, R. Stewart, J. Becker
FPGA Startup Through Sequential Partial and Dynamic Reconfiguration (Link)
In VLSI 2010 Annual Symposium, Band 105, S. 289-302, 2011 - C. Roth, O. Sander, M. Kuehnle, J. Becker
Flexible and Efficient Co-Simulation of Networked Embedded Devices
In 24th Symposium on Integrated Circuits and Systems Design, João Pessoa - Brazil, 2011 - J. E. Becker, O. Sander, A. Klimm, S. Bulach, K. Weinberger, J. Becker
Towards Provable Protocol Conformance of Serial Automotive Communication IP (Link)
In Design & Verification Conference & Exhibition (DVCon), 2011 - C. Roth, O. Sander, G. Almeida, L. Ost, N. Hebert, G. Sassatelli, P. Benoit, L. Torres, J. Becker
Modular Framework for Multi-level Multi-device MPSoC Simulation
In IEEE International Symposium on Parallel and Distributed Processing, 2011. IPDPS 2011., 2011 - C. Roth, O. Sander, M. Kuehnle, J. Becker
HLA-based Simulation Environment for distributed SystemC Simulation
In 4th International ICST Conference on Simulation Tools and Techniques (SIMUTools 2011) , Barcelona, Spain, 2011 - J. Meyer, J. Noguera, M. Huebner, L. Braun, O. Sander, R. Mateos Gil, R. Stewart, J. Becker
Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration
In Design, Automation and Test in Europe (DATE '11), S. 6, 2011
