In previous research projects, ITIV has developed the V-FPGA, an FPGA architecture that was primarily designed as a virtualization layer for commercial FPGAs. This FPGA architecture mostly consists of basic building blocks: Lookup Tables, flip-flops and it constitutes a generic, general purpose base FPGA architecture. To make use of a custom FPGA, in addition to the FPGA hardware architecture a toolchain which synthesizes HDL code for this architecture is required. We use the VTR/VPR toolchain for this, with some individual customizations.
Any topic related to FPGA architectures may be considered for a bachelor or master thesis: This includes adaptations to the buildings blocks (specific DSP blocks, custom data formats, specific memory blocks), the interconnect (e.g. Network-on-Chip based architectures) and application driven architecture optimizations (e.g. optimizing an FPGA architecture for machine learning applications).
Apart from these hardware topics, I‘d also be happy to supervise any thesis focusing on synthesis algorithms or tools. An example here might be using quantum annealing algorithms instead of simulated annealing, designing mapping algorithms for heterogeneous reconfigurable blocks and similar topics.