In previous research projects, ITIV has developed the V-FPGA, an in-house, custom FPGA architecture. The VFPGA is largely based on lookup tables (LUTs), a reconfigurable hardware block which can implement any Boolean function of n inputs. In addition, in the PARFAIT project we are researching reconfigurable universal logic modules (ULM) which can only be reconfigured to a set of different, predetermined functions. Whereas synthesis to LUTs is a well-known problem (commercial FPGAs) and synthesis to ULMs is isomorphic to standard cell synthesis, synthesis to hybrid LUT/ULM systems is mostly unresearched.
The main task of this thesis is to investigate possible algorithms and synthesis strategies for synthesis onto mixed ULM/LUT architectures. The hybrid architecture is available as an VPR architecture model and tool flows mapping on the ULM or LUT part are available. As part of the thesis, first research and comparison of existing algorithms for such hybrid synthesis problems needs to be done. Then a concept shall be implemented how to adapt this to the VPR Toolflow. Ultimately an evaluation of the synthesis results shall be carried out, comparing the results to ULM only / LUT only results.
- C/C++ knowledge recommended
- Basic knowledge of bash scripts and Linux will be useful