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Designing a Power Domain aware FPGA

Designing a Power Domain aware FPGA
Typ:Masterarbeit
Datum:offen (zu vergeben)
Betreuer:

M. Sc. Johannes Pfau

Designing a Power Domain aware FPGA

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Context

In previous research projects, ITIV has developed the V-FPGA, an in-house, custom FPGA architecture. For testing purposes, the VFPGA can be synthesized onto commercial FPGA hardware. Currently, the VFPGA design is not using any power optimization. The PARFAIT technology used for the FPGA however allows to scale the threshold voltage of transistors to balance static and dynamic power, static power and switching performance.

 

 

Task

The main task of this thesis is to investigate ways to dynamically adjust the voltage for certain areas of the FPGA. The VFPGA architecture shall be extended for this (e.g. how many different voltage levels, granularity of the approach) according to literature research and a developed concept. Then the changes shall be implemented in the VFPGA RTL and the VPR toolchain shall be extended to output information about the required switching performance (e.g. which areas on the FPGA are unused, …). In the end, various test applications shall be developed to demonstrate the power management system.

 

 

Prerequisites

VHDL knowledge recommended